Cladding Layer Controls Gate Critical Dimension Uniformity

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Solution Overview

Problem

Semiconductor devices face challenges in achieving critical dimension uniformity during the fabrication process, particularly as devices continue to shrink in size, leading to inconsistencies and reduced performance.

Innovation Solution

The use of a cladding layer, which can be formed before or after filling a recess in an active channel structure with dielectric material, provides consistent and larger process windows for forming gate structures in integrated circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If semiconductor devices continue to decrease in size, then device scaling and integration density improve, but critical dimension uniformity deteriorates

Engineering Contradiction:

Improvedevice sizeVSAvoidcritical dimension uniformity

Core Design Contradiction:

Volume of moving objectVSManufacturing precision

Solution Approach 1:

The cladding layer is formed in advance before the gate patterning process. This preliminary action creates a controlled structural feature that defines the gate critical dimension, allowing the gate width to be determined by the cladding layer thickness rather than direct patterning, thereby improving critical dimension uniformity as devices scale down

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The invention changes the physical parameter of the cladding layer thickness to directly control the gate critical dimension. By adjusting this thickness parameter through deposition control, the gate width is precisely defined, enabling consistent critical dimensions even as overall device size decreases

Inventive Principle:

Principle #35Parameter changes

2Manufacturing precision

If a cladding layer is formed around the active channel structure, then critical dimension uniformity improves, but device complexity increases

Engineering Contradiction:

Improvecritical dimension uniformityVSAvoidstructure complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The semiconductor structure is segmented into distinct functional layers, with the cladding layer being a separate, discrete structure formed around the active channel. This segmentation allows the cladding layer to be independently controlled and removed, providing critical dimension definition without permanently complicating the final device structure

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The cladding layer is introduced as a temporary structural element that is formed, used for definition, and then completely removed after serving its purpose. This extraction approach allows the cladding layer to provide critical dimension control during fabrication without remaining as part of the final device structure, thus avoiding permanent complexity

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS20250120151A1Process window control for gate formation in semiconductor devices

Publication Date: 2025.04.10 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method of fabricating a semiconductor structure includes forming a recess in an active channel structure by removing a portion thereof, filling the recess with a dielectric material, forming a cladding layer adjacent the active channel structure but not adjacent the dielectric material, and forming a gate structure comprising a first gate structure and a second gate structure around the active channel structure. A width of the dielectric material in the recess is greater than a width of the first gate structure and a width of the second gate structure.