Clamp Output Buffer for Reduced Swing and Shared Pad I/O
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Solution Overview
Problem
CMOS output buffers face challenges in maintaining signal amplitude and drive capability when power saving methods reduce the output signal amplitude, leading to signal waveform deterioration and increased load capacity issues, while also requiring separate pad electrodes for input and output buffers, resulting in a higher number of pad electrodes.
Innovation Solution
The integration of a clamp output stage with a field effect transistor for potential clamp between P-channel and N-channel transistors, allowing the output buffer to operate with an intermediate signal level and sharing pad electrodes between input and output buffers by using a data input part connected to the clamp output stage, which inputs data signals based on an enable signal during data output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If power saving method is used to reduce output signal amplitude, then power consumption is reduced, but drive capability deteriorates and signal waveform quality decreases
Solution Approach 1:
The output buffer dynamically adjusts its operating mode between full swing mode (for high drive capability) and intermediate level mode (for power saving) based on the enable signal state. This dynamic switching allows the system to optimize between power consumption and signal quality requirements differentially across time
Solution Approach 2:
The invention changes the output signal amplitude parameter by introducing an intermediate level between the high power supply potential and low power supply potential. The clamp transistor actively controls the output voltage to transition between full swing (0 to VDD) and reduced swing (intermediate level to VDD), thereby adjusting power consumption while maintaining signal integrity when needed
2Reliability
If separate pad electrodes are provided for input and output buffers, then signal integrity is maintained, but the number of pad electrodes increases
Solution Approach 1:
The pad electrode is designed to serve multiple functions by being shared between the input buffer and output buffer. The enable signal mechanism allows the same physical pad to alternatively receive input signals or provide output signals, eliminating the need for separate dedicated pad electrodes for each buffer type
Solution Approach 2:
The pad electrode dynamically switches its functional role between input and output modes based on the enable signal state. When the enable signal is active, the pad functions as an output; when inactive, it functions as an input, allowing one pad to replace what would traditionally require two separate pads
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution maintains signal amplitude and drive capability while reducing power consumption and the number of pad electrodes by allowing the output buffer to operate with an intermediate signal level and enabling shared pad usage, thus addressing power saving and signal integrity issues.
Implementation Method 1
A field effect transistor for potential clamp is inserted in series between a P-channel field effect transistor and an N-channel field effect transistor and an intermediate level between a high potential supplied to a source of the P-channel field effect transistor and a low potential supplied to a source of the N-channel field effect transistor is input into a gate of the field effect transistor for potential clamp so that the clamp output stage clamps a drain potential of the P-channel field effect transistor or a drain potential of the N-channel field effect transistor
Data Source
AI summary
According to one embodiment, a clamp transistor is inserted in series between a P-channel field effect transistor and an N-channel field effect transistor and an intermediate level between a high potential supplied to a source of the P-channel field effect transistor and a low potential supplied to a source of the N-channel field effect transistor is input into a gate of the clamp transistor to clamp a drain potential of the N-channel field effect transistor.