Clamp Transistor Threshold Voltage Variation Reduction
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Solution Overview
Problem
Current semiconductor memory devices, particularly MRAM, face challenges in reducing variations in threshold voltage of transistors, leading to signal errors and increased leakage currents, which affect the reliability of read operations.
Innovation Solution
The design incorporates a clamp transistor with specific impurity diffusion regions and a gate structure that reduces variations in threshold voltage by applying a substrate bias voltage, thereby minimizing junction leakage and gate-induced drain leakage, and optimizing the placement of impurity diffusion regions to decrease re-diffusion and drain-induced barrier lowering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate length is reduced to increase productivity, then the manufacturing precision deteriorates due to increased variations in threshold voltage
Solution Approach 1:
The patent introduces a lightly-doped drain (LDD) structure with a specific impurity concentration gradient in the channel region. This creates local quality variations where the impurity concentration is higher near the source/drain junctions and lower in the channel center, thereby reducing threshold voltage variations without increasing the overall gate length. The LDD structure allows different regions of the transistor to have optimized properties for their specific functions.
Solution Approach 2:
The patent changes the impurity concentration parameter by introducing a lightly-doped drain region with controlled impurity levels. By adjusting the impurity concentration in the LDD region (lower than the source/drain region but higher than the channel center), the threshold voltage can be precisely controlled. This parameter change enables reduced gate length while maintaining threshold voltage uniformity across the transistor array.
2Productivity
If the gate length is reduced to increase productivity, then the reliability deteriorates due to increased signal errors and leakage currents
Solution Approach 1:
The LDD structure creates local quality variations in the channel region, with higher impurity concentration near the source/drain junctions to reduce leakage currents and lower impurity concentration in the channel center to maintain threshold voltage control. This local optimization improves reliability by reducing both signal errors and leakage currents while allowing for reduced gate length and increased productivity.
Solution Approach 2:
The lightly-doped drain region acts as a cushioning layer between the heavily-doped source/drain regions and the channel. This LDD structure beforehand cushions against the harmful effects of high impurity concentrations, reducing junction leakage currents and preventing threshold voltage variations before they can affect transistor operation and reliability.
3Manufacturing precision
If ion implantation is used to increase manufacturing precision, then the reliability deteriorates due to ion implantation damage
Solution Approach 1:
The patent changes the impurity concentration parameter by creating a gradient distribution rather than uniform doping. The LDD structure has lower impurity concentration than conventional heavily-doped drains, reducing ion implantation damage. By precisely controlling the impurity concentration in different regions (higher at junctions, lower in channel), the patent achieves both manufacturing precision and improved reliability.
Solution Approach 2:
The patent converts the potential harm of ion implantation damage into a benefit by using a lightly-doped drain structure. Instead of using high-energy ion implantation that causes damage, the LDD structure uses lower impurity concentrations that reduce damage while still achieving the desired electrical characteristics. The moderate doping in the LDD region provides the benefits of impurity control without the harmful effects of heavy ion implantation.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a memory cell, a bit line connected to the memory cell, a sense circuit which senses data of the memory cell based on second current that flows through the memory cell and first current, a first transistor of a first conductivity type, which is connected to the bit line and through which the second current flows, and a second transistor of the first conductivity type, through which the first current flows.