Clamped Phase Interpolator for Low-INL Clock Capture
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Solution Overview
Problem
Phase interpolators in digital logic circuits suffer from non-linearity issues, leading to unequal phase increments and increased bit error rates due to transistor non-linearity, making it difficult to synchronize data capture at optimal phases.
Innovation Solution
A clamped phase interpolator with a clamping circuit that adjusts operation to a limited range of integral non-linearity, using a reduced range of interpolation codes to generate an interpolated clock with improved bit error rate (BER) by adjusting the target phase within a reduced phase range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a phase interpolator divides the phase range into equal increments, then the phase distribution should be uniform, but transistor non-linearity causes some increments to be too narrow and some too wide
Solution Approach 1:
The patent changes the parameter of phase range to a limited range (e.g., 45 degrees instead of full 360 degrees) where the PI circuit exhibits better linearity. This parameter change allows the phase interpolator to operate in a region where transistor non-linearity has minimal impact on phase increment uniformity.
Solution Approach 2:
The patent introduces dynamic adjustment mechanisms including a clamping circuit that dynamically limits the phase range, and calibration circuits that dynamically adjust interpolation codes to compensate for non-linearity. These dynamic adjustments maintain phase increment uniformity across operating conditions.
2Adaptability or versatility
If the phase range is extended to cover all possible phases, then the versatility of data capture is improved, but the bit error rate increases due to non-linearity
Solution Approach 1:
The patent segments the full phase range into multiple limited ranges, each with its own calibration parameters or interpolation code sets. By dividing the operation into segments, each operating in a optimized phase range, the system maintains low bit error rates while achieving comprehensive phase coverage through selective segment activation.
Solution Approach 2:
The patent introduces intermediary calibration circuits and lookup tables that mediate between the desired phase and the actual PI output. These intermediaries translate target phase values into corrected interpolation codes, ensuring accurate phase generation within the limited range while maintaining system versatility.
3Manufacturing precision
If calibration is performed across the full range of interpolation codes, then comprehensive linearity correction is achieved, but the complexity and time required for calibration increases
Solution Approach 1:
The patent extracts only the critical portion of the interpolation code range that corresponds to the limited phase range where operation actually occurs. By taking out and calibrating only this essential subset of codes, the system achieves sufficient linearity correction without the complexity of calibrating the entire code range.
Data Source
AI summary
A phase-interpolator (PI) circuit generates an interpolated clock to capture data in a capture circuit at a target phase in a phase range between two reference clocks based on an interpolation code within a range of interpolation codes is described. A clamping circuit coupled to the PI circuit provides an interpolation code within a reduced range, where the integral non-linearity (INL) of the interpolated clocks is below a threshold, such that data capture based on the interpolated clock has a lower bit error rate (BER). As a result, the interpolated clock is generated within a reduced phase range corresponding to the reduced range of interpolation codes. When a target phase for an interpolated clock is outside the reduced phase range, the clamping circuit may adjust the target phase clock relative to a reference clock to adjust the target phase to be within the reduced phase range for improved BER.