Clamping Circuit for Parasitic Transistor Leakage Current

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Solution Overview

Problem

High-voltage and high-current applications face challenges with parasitic transistors experiencing leakage current, leading to latch-up events that can cause damage and thermal runaway in power electronic devices like MOSFETs and IGBTs, especially in elevated temperature environments.

Innovation Solution

A clamping circuit with a current sensor and current multiplier is introduced to sense and reduce leakage current in parasitic transistors, using a combination of MOSFETs and parasitic components to clamp voltage levels and prevent latch-up events by injecting or drawing current proportionally to the sensed leakage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If power MOSFETs are used for high-voltage and high-current applications, then power delivery capability is improved, but leakage current in parasitic transistors increases causing latch-up events

Engineering Contradiction:
Improvepower delivery capabilityVSAvoidoperational stability
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The patent implements a feedback mechanism where a sensing transistor detects leakage current in parasitic transistors, and this information is fed back to control circuitry that activates clamp circuits to counteract the leakage, preventing latch-up events while maintaining high-power operation

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent introduces intermediary components including sensing transistors, clamp circuits, and control logic that mediate between the power MOSFETs and the parasitic leakage paths, allowing high-power operation while actively managing and suppressing leakage current through these intermediary elements

Inventive Principle:
Principle #24Intermediary (Mediator)

2Power

If power MOSFETs operate at elevated temperatures, then power delivery is maintained, but leakage current increases leading to thermal runaway

Engineering Contradiction:
Improvepower deliveryVSAvoidoperating temperature stability
Core Design Contradiction:
PowerVSTemperature

Solution Approach 1:

The sensing transistor continuously monitors leakage current which increases with temperature, and the control circuitry responds by activating clamp circuits that inject compensating currents, creating a feedback loop that stabilizes operation even at elevated temperatures

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent implements preliminary protective measures by continuously monitoring for conditions that precede thermal runaway and activating clamp circuits in advance to counteract increasing leakage current before it can cause thermal runaway or device damage

Inventive Principle:
Principle #9Preliminary anti-action

3Reliability

If clamp circuits are added to reduce leakage current, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improveprotection from latch-upVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The sensing transistor automatically detects leakage current conditions and triggers the clamp circuits without requiring external control, allowing the system to protect itself from latch-up events while minimizing the need for complex external control circuitry

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10944394B2Methods and apparatus to reduce leakage current
Publication Date: 2021.03.09 TEXAS INSTRUMENTS INC
  • US10944394B2 patent drawing
  • US10944394B2 patent drawing
  • US10944394B2 patent drawing

AI summary

Methods, apparatus, systems and articles of manufacture are disclosed that provide an apparatus comprising: a first transistor including a first gate, a first current terminal, and a second current terminal; a second transistor including a second gate, a third current terminal, and a fourth current terminal; the first current terminal coupled to the third current terminal; the first gate coupled to the second gate and the second current terminal; a third transistor including a third gate, a fifth current terminal, and a sixth current terminal, the fifth current terminal coupled to the second current terminal, third gate coupled to a voltage reference node; and a fourth transistor including a fourth gate, a seventh current terminal and an eighth current terminal, the seventh current terminal coupled to the sixth current terminal, the fourth gate coupled to the seventh current terminal and the eighth current terminal coupled to the fourth current terminal.