Clamping Voltage Generation Circuit for Nonvolatile Memory Read Reliability

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Solution Overview

Problem

Nonvolatile memory devices, such as MRAMs, face challenges in maintaining reliability due to variations in memory cell resistance values and external reference voltages, which affect data read operations.

Innovation Solution

A nonvolatile memory device with a clamping circuit and clamping voltage generation unit that adjusts the clamping voltage based on reference voltages from reference cells, ensuring consistent data sensing and amplification, thereby improving read operation reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a fixed clamping voltage is used in the clamping circuit, then the circuit structure is simple, but the read operation reliability deteriorates due to variations in memory cell resistance values

Engineering Contradiction:
Improveread operation reliabilityVSAvoidclamping voltage generation unit
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies dynamics by transitioning from a fixed clamping voltage to a variable clamping voltage that dynamically adapts to changes in memory cell resistance. The clamping voltage generation unit continuously adjusts the clamping voltage based on feedback from the memory cell's actual resistance state, enabling the system to maintain optimal read operation reliability under varying conditions.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements feedback by incorporating a feedback path that monitors the actual voltage level at the data sensing line and uses this information to adjust the clamping voltage. The clamping voltage generation unit receives feedback signals and modifies the clamping voltage accordingly, creating a closed-loop control system that maintains reliable read operations despite resistance variations.

Inventive Principle:
Principle #23Feedback

2Reliability

If the clamping voltage is adjusted to compensate for resistance variations, then read operation reliability improves, but the device complexity increases

Engineering Contradiction:
Improvedata read reliabilityVSAvoidclamping circuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies universality by designing the clamping voltage generation unit to serve multiple functions: it generates the clamping voltage, adjusts it based on feedback, and compensates for resistance variations all within a single integrated circuit block. This multi-functional approach improves reliability while minimizing the increase in device complexity by consolidating functions rather than adding separate components.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Measurement precision

If reference cells are added to generate reference voltages, then data sensing accuracy improves, but the memory device area increases

Engineering Contradiction:
Improvedata sensing accuracyVSAvoidmemory device area
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent applies local quality by placing reference cells at specific strategic locations within the memory array rather than distributing them uniformly throughout. The reference cells are positioned at key intersection points where they can most effectively provide reference voltages for nearby memory cells, thereby improving sensing accuracy in critical regions while minimizing the overall area occupied by reference structures.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS8654595B2Nonvolatile memory device with a clamping voltage generation circuit for compensating the variations in memory cell parameters
Publication Date: 2014.02.18 SAMSUNG ELECTRONICS CO LTD
  • US8654595B2 patent drawing
  • US8654595B2 patent drawing
  • US8654595B2 patent drawing

AI summary

A nonvolatile memory device comprises a nonvolatile cell array comprising a memory cell and a reference cell, a clamping circuit electrically connected to the memory cell and configured to clamp a voltage applied to a data sensing line during a read operation, and a clamping voltage generation unit configured to generate a clamping voltage responsive to a first voltage having a level based on the reference cell, and to feed back the clamping voltage to the clamping circuit.