Class AB Amplifier Circuit With Low Offset and High Gain
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Solution Overview
Problem
Existing amplifiers face challenges in achieving high voltage gain, low input offset voltage, and efficient class AB operation while maintaining low bias current and large peak current capability, especially when driving capacitive loads with rail-to-rail output voltage swing.
Innovation Solution
The design incorporates a class AB amplifier circuit with two high impedance nodes and a translinear harmonic mean regulating feedback loop, utilizing folded double cascode stages and precision biased output transistors to enhance voltage gain and reduce input offset voltage, allowing for equal gain on both positive and negative signal swings and efficient capacitive load driving.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If class AB amplifier operation is implemented, then amplification efficiency is improved, but distortion of input waveforms increases compared to class A
Solution Approach 1:
The amplifier is divided into two separate class AB amplifier circuits (first and second class AB amplifier circuits) that operate in a push-pull configuration. Each circuit handles one half of the input signal waveform, with first output transistor pair handling positive half-cycles and second output transistor pair handling negative half-cycles. This segmentation allows efficient class AB operation while maintaining waveform integrity through complementary operation.
Solution Approach 2:
The patent combines features of class A (low distortion) and class B (high efficiency) by merging two class AB amplifier circuits operating in complementary fashion. The first and second class AB amplifier circuits are merged through their shared input terminal and complementary output stages, achieving both low distortion and high efficiency simultaneously.
2Power
If voltage gain is increased to achieve high amplification, then amplification efficiency is improved, but input offset voltage increases
Solution Approach 1:
The patent employs asymmetric folded cascode amplifier stages with carefully designed current mirror configurations and biasing circuits. The first and second folded cascode amplifier stages use different transistor pairs (first and second output transistor pairs) with complementary characteristics, creating an asymmetric structure that compensates for offset voltages while maintaining high voltage gain through the cascaded amplifier stages.
Solution Approach 2:
The patent implements feedback mechanisms through the coupled operation of the first and second class AB amplifier circuits. The complementary push-pull configuration provides inherent feedback where each circuit compensates for the other's deviations, reducing input offset voltage while maintaining high voltage gain through the interconnected amplifier stages.
3Use of energy by moving object
If bias current is reduced to improve power efficiency, then energy consumption is improved, but peak current capability decreases
Solution Approach 1:
The patent employs dynamic current management in the folded cascode amplifier stages and output transistor pairs. The biasing circuits provide low quiescent bias current for power efficiency, while the amplifier stages are designed to dynamically increase current delivery during peak signal conditions. The coupled class AB configuration allows each transistor pair to operate efficiently at low bias while providing high peak current capability when needed.
4Adaptability or versatility
If output voltage swing is extended to achieve rail-to-rail operation, then adaptability is improved, but distortion increases
Solution Approach 1:
The output voltage swing range is segmented between the first and second class AB amplifier circuits, with each circuit optimized for its respective half of the output range. The first output transistor pair handles the positive voltage swing toward the first rail, while the second output transistor pair handles the negative voltage swing toward the second rail. This segmentation allows rail-to-rail operation without excessive distortion in either direction.
Data Source
AI summary
An amplifier circuit including a first folded double cascode stage configured to receive a differential input signal at a first pair of input transistors and generate a first drive signal, a second folded double cascode stage configured to receive the differential input signal at a second pair of input transistors and generate a second drive signal, and an output stage. The output stage includes a PMOS common-source output transistor configured to receive the first drive signal at its gate, and an NMOS common-source output transistor configured to receive the first drive signal at its gate, the PMOS common-source output transistor and NMOS common-source output transistor being jointly configured to generate an output signal based on the first drive signal and the second drive signal.