Class AB Op-Amp Driver Circuit for Higher Output Current
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Solution Overview
Problem
Two-stage class AB operational amplifiers face limitations in providing maximum current to resistive loads due to the quadratic relationship between MOS drain current and gate-source voltage, leading to restricted output current during positive waveform portions.
Innovation Solution
The proposed solution involves a driving circuit with a PMOS and NMOS transistor configuration, where a resistor network ensures a fixed voltage drop, allowing for increased output current by maintaining high impedance gate terminals for output transistors, thus overcoming the current limitations of prior art.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a current mirror is used to drive the output stage, then the dc biasing current can be controlled, but the maximum output current is limited to two times the dc current
Solution Approach 1:
The patent removes the current mirror configuration from the driving circuit, directly connecting the input stage output to the output stage inputs. This extraction eliminates the current limitation imposed by the current mirror while reducing circuit complexity.
Solution Approach 2:
Instead of using a current mirror to control and limit the output current, the patent inverts the approach by allowing the output stage to draw current directly from the input stage, enabling the output current to exceed the dc biasing current without the 2x limitation.
2Power
If the output stage is directly driven by the input stage, then the current limitation is overcome, but the gate terminals of output transistors become low impedance nodes
Solution Approach 1:
The patent introduces resistors connected to the gate terminals of the output transistors as intermediary elements. These resistors maintain high impedance at the gate terminals while still allowing the output stage to be driven by the input stage, thus preserving both high output current capability and proper gate terminal characteristics.
3Ease of manufacture
If MOS transistors are used in the output stage, then integration is achieved, but the quadratic relationship between drain current and gate-source voltage limits output current
Solution Approach 1:
The patent employs dynamic biasing of the output stage using resistors that allow the gate-source voltages of the MOS transistors to vary dynamically. This dynamic operation enables the output current to exceed the dc biasing current by utilizing the quadratic relationship between drain current and gate-source voltage in a controlled manner, rather than being limited by it.
Data Source
AI summary
The invention relates to a two stage class AB operational amplifier for driving a load, comprising at least an input stage comprising differential input terminals and an output terminal to provide a driving signal. In addition, the operational amplifier comprises an output stage comprising a first and second input terminals operatively associated to the input stage to be driven on the basis of said driving signal and a driving circuit operatively interposed between said input stage and the output stage. The operational amplifier is characterized in that the driving circuit comprises a first portion comprising at least one resistor operatively connected between a first reference potential via a first circuitry block comprising a PMOS transistor and a second reference potential via a second circuitry block comprising a NMOS transistor. The voltage drop on said at least a first resistor is fixed to a value depending on said first and second reference potentials and the gate-source voltages of said PMOS and NMOS transistors, respectively. The driving circuit further comprises a second portion comprising a first resistor and a second resistor having first terminals connected one another in a common terminal which is connected to the output terminal of the input stage. Said first resistor has a second terminal connected the first input terminal of the output stage and said second resistor has a second terminal connected to the second input terminal of the output stage. Said second terminals of the first and second resistors (R2′) are connected to the first reference potential via a third circuitry block and to the second reference potential (GND) via a fourth circuitry block, respectively. Said third (MW, M9) and fourth (M10, MX) circuitry blocks are arranged to be operatively connected to said first and second circuitry blocks, respectively, so that the voltage drop between the second terminals is substantially equal to the value of the voltage drop (VR1) across said at least one resistor.