Class-AB Driver Speed Balancing for Improved Frequency Response
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Class-AB drivers for wideband applications face reduced frequency response performance due to imbalanced signal traveling paths, leading to close-in left-half-plane zeros that result in drooping in-band frequency response and low out-of-band attenuation.
Innovation Solution
Incorporating a speed balancing resistor or additional transistors in the trans-linear loop to equalize signal travel times between the upper and lower signal paths, either by adding a resistor between nodes A and B or using transistors M10 and M11 to match the speed of the signal paths, thereby canceling out the close-in zero and improving frequency response.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a trans-linear loop is used for easy biasing implementation, then biasing ease is improved, but signal path imbalance occurs causing close-in LHP zero that reduces frequency response performance
Solution Approach 1:
A speed balancing resistor is introduced as an intermediary element in the faster signal path (upper path) to equalize the signal travel times between the two paths. This mediator component compensates for the inherent imbalance without requiring complete redesign of the trans-linear loop structure, thus maintaining biasing ease while improving frequency response performance by eliminating the close-in LHP zero.
2Reliability
If signal path speed balancing is implemented to cancel close-in zero, then frequency response performance is improved, but device complexity increases due to additional components
Solution Approach 1:
The speed balancing resistor is placed locally only in the faster signal path (upper path) where it is needed to equalize signal travel times. This localized modification rather than global circuit redesign achieves the frequency response improvement with minimal additional complexity, adding only one component to the existing trans-linear loop structure.
Data Source
AI summary
A class-AB driver design with improved frequency response is disclosed. In one embodiment, the class-AB driver includes a push-pull output stage, a trans-linear loop, an input stage, a current biasing and enabling circuit. Further, the trans-linear loop is coupled to a signal input terminal ABIN via node A, and the push-pull output stage is coupled to the trans-linear loop via node B and node C. Further, the trans-linear loop includes a speed balancing resistor RB in a faster signal traveling path (i.e., ABIN to ABOUT via node A and B) to match up the speed with a slower signal traveling path (i.e., ABIN to ABOUT via node A and C). In another embodiment, the MOS transistors are also used instead of the speed balancing resistor RB to balance the signal traveling time of the two signal traveling paths.