Class AB Operational Amplifier With Dual-Voltage Locking Prevention
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Solution Overview
Problem
Existing operational amplifiers face challenges in achieving low noise, low power consumption, and small area due to the limitations of NMOS FET and PMOS FET input stage circuits, with class AB input stage circuits offering potential improvements but facing issues of locking and inefficient power management.
Innovation Solution
The operational amplifier design incorporates a first-stage and second-stage amplification circuit architecture, utilizing a class AB input stage circuit with distinct power voltage levels, where the first-stage operates at a higher voltage than the second-stage, preventing locking and enabling efficient power management through current source reuse and feedback mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If NMOS FET or PMOS FET input stage circuit is used, then device complexity is reduced, but noise increases and power consumption increases
Solution Approach 1:
The input stage is divided into two parallel branches: NMOS input pair (first transistor and second transistor) and PMOS input pair (third transistor and fourth transistor). Each branch processes signals independently and contributes to the overall output, allowing noise reduction through differential operation while maintaining relatively simple individual branch structures
Solution Approach 2:
The patent combines NMOS and PMOS input pairs in a unified class AB configuration, merging the advantages of both transistor types. The current sources and biasing circuits are shared between the two branches, reducing overall device complexity while achieving low noise performance through the complementary structure
2Object-generated harmful factors
If class AB input stage circuit is used, then noise is reduced and power consumption is reduced, but locking issue occurs
Solution Approach 1:
Different voltage levels are applied to different parts of the circuit: the first power voltage (first voltage level) is applied to the NMOS input pair branch, while the second power voltage (second voltage level, lower than first) is applied to the PMOS input pair branch. This local differentiation prevents locking by ensuring proper voltage headroom in each branch while maintaining the class AB low-noise architecture
Solution Approach 2:
The patent changes the power voltage parameter from a single uniform voltage to two distinct voltage levels. By adjusting the voltage level for each branch, the circuit operates in optimal regions for both NMOS and PMOS transistors, preventing saturation and locking while preserving the low noise characteristics of class AB operation
3Device complexity
If single power voltage is used for both stages, then device complexity is reduced, but performance optimization is limited
Solution Approach 1:
The power management system transitions from static single-voltage operation to dynamic multi-voltage operation. The first-stage operational amplifier receives the first power voltage optimized for high-speed operation, while the second-stage operational amplifier receives the second power voltage optimized for its specific load and frequency range, allowing each stage to operate at optimal performance levels
Data Source
AI summary
An operational amplifier includes a first power voltage end, a second power voltage end, a first-stage operational amplification circuit, and a second-stage operational amplification circuit. The first power voltage end is configured to receive a first power voltage signal, the second power voltage end is configured to receive a second power voltage signal, and a voltage value of the first power voltage signal is greater than a voltage value of the second power voltage signal. The first-stage operational amplification circuit is configured to receive an input signal via a signal input end, and amplify the input signal under enabling control of the first power voltage signal, to generate a first drive signal. The second-stage operational amplification circuit is configured to generate an output signal.