Class-D Amplifier Test Mode Using a Sigma-Delta ADC Loop

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Solution Overview

Problem

The high cost and limited space constraints of industrial testing for Class-D amplifiers in parallel testing setups, combined with noisy environments that complicate sensitive audio measurements, necessitate a more efficient and integrated solution for testing these amplifiers.

Innovation Solution

An integrated circuit with a Class-D amplifier that can switch between operational and test modes, reconfiguring the PWM control loop as a second-order ΣΔ ADC by incorporating a sampler and feedback network, eliminating the need for external ADCs and mitigating noise effects, thereby reducing hardware requirements and improving measurement quality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If external ADCs and low-pass filters are added to the test setup for audio measurements, then measurement precision is improved, but device complexity and cost increase

Engineering Contradiction:
Improveaudio measurement precisionVSAvoidtest setup complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent merges the ADC and low-pass filter functions into the Class-D amplifier itself by reconfiguring the PWM control loop as a second-order ΣΔ ADC. The comparator, integrators, and sampler within the amplifier perform both audio filtering and digital conversion, eliminating the need for separate external ADCs and LPFs in the test setup.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The amplifier's internal components serve multiple functions: the integrators act as both audio low-pass filters during normal operation and as part of the ΣΔ ADC structure during testing. The comparator and sampler work together for both PWM generation and digital signal conversion, allowing the same hardware to perform multiple roles.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If multiple amplifiers are tested in parallel on a handler, then productivity is improved, but the limited space on the handler worsens

Engineering Contradiction:
Improvetesting throughputVSAvoidhandler space
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

By integrating the ADC and filtering functions into each amplifier, the patent eliminates the need for separate external ADCs and LPFs that would occupy significant space on the handler. This consolidation allows more amplifiers to be tested in parallel within the same physical footprint.

Inventive Principle:
Principle #5Merging (Combining)

3Device complexity

If the amplifier is tested in operational mode with direct comparator coupling to output stage, then device complexity is reduced, but measurement reliability deteriorates due to noisy environment

Engineering Contradiction:
Improvetest configuration simplicityVSAvoidmeasurement reliability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent implements a dynamic test mode that reconfigures the amplifier's internal connections during testing. The sampler is enabled to couple the comparator to the output stage via the feedback network, transforming the amplifier into a ΣΔ ADC configuration only when needed for measurements, while maintaining the simpler operational mode for normal function.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The reconfigured test mode utilizes the existing feedback network to create a closed-loop ΣΔ ADC structure. The feedback path carries the digital signal from the sampler back through the integrators and comparator, providing the necessary feedback for accurate audio measurements while rejecting environmental noise.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8502601B2Integrated circuit
Publication Date: 2013.08.06 GOODIX TECH HK CO LTD
  • US8502601B2 patent drawing
  • US8502601B2 patent drawing
  • US8502601B2 patent drawing

AI summary

An integrated circuit comprising a Class-D amplifier for amplifying an input signal at an input terminal is disclosed. The Class-D amplifier is switchable between an operational mode, in which a comparator (4) is directly coupled to an output stage (5), and a test mode, in which the comparator (4) is coupled to the output stage (5) via a sampler (15) and the output stage (5) is coupled to the input terminal via a feedback network, whereby a digital representation of the input signal is available at an output of the sampler (15).