Class D Amplifier Sampling Rate Conversion for Low-Jitter Audio
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Solution Overview
Problem
Class D amplifiers require stable, low jitter system clocks to produce analog output signals with acceptable noise and distortion characteristics, but existing solutions, such as Class-AB power amplifiers, are inefficient and costly, and Class D amplifiers often fail to meet audio quality requirements due to stringent system requirements.
Innovation Solution
A Class D amplifier circuit incorporating a sampling rate converter, pulse width modulator, sigma-delta modulator, and PWM pulse generator, which up-samples the input signal, performs sigma-delta modulation, and generates pulses with widths proportional to the audio signal amplitude, allowing for programmable parameters to optimize audio output characteristics and minimize spurious tones.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If Class-AB power amplifiers are used to meet analog output signal noise and distortion requirements, then audio quality is improved, but power efficiency and die area deteriorate
Solution Approach 1:
The patent changes the operating parameters of the amplifier by using Class D topology with pulse width modulation instead of Class-AB linear amplification. The PWM technique converts the analog signal to digital domain, allowing efficient switching operation while maintaining audio quality through controlled pulse width variation that preserves signal fidelity.
Solution Approach 2:
The patent replaces the traditional analog feedback control mechanism of Class-AB amplifiers with a digital control system using PWM modulation. This substitution of control methodology eliminates the need for high-power linear operation, achieving both efficiency and audio quality through digital signal processing and switching control.
2Loss of energy
If Class D amplifiers are used to improve power efficiency, then power consumption is reduced, but system complexity and calibration requirements increase
Solution Approach 1:
The patent implements self-calibration capability within the Class D amplifier system, where the amplifier automatically adjusts its parameters to achieve optimal performance without requiring external calibration equipment or complex manual procedures. This self-service approach reduces system complexity while maintaining the power efficiency benefits of Class D operation.
Solution Approach 2:
The patent integrates multiple functions into a single Class D amplifier chip, combining PWM modulation, digital signal processing, and output control in one unified device. This multi-functionality reduces the need for separate calibration systems and external components, simplifying the overall system while preserving power efficiency.
3Manufacturing precision
If stable low jitter system clocks are used in Class D amplifiers to reduce spurious tones, then audio quality is improved, but system cost and complexity increase
Solution Approach 1:
The patent introduces an intermediary digital signal processing stage that mediates between the clock signal and the output waveform. This intermediary processing allows the use of less stringent clock signals while still achieving low spurious tone levels, as the digital processing compensates for clock imperfections through algorithmic correction and filtering.
Solution Approach 2:
The patent uses digital copying and reconstruction techniques where the original analog signal is converted to digital form, processed through PWM modulation, and then reconstructed at the output. This copying process in the digital domain allows for error correction and spurious tone reduction without requiring ultra-stable analog clocks, reducing system complexity.
Data Source
AI summary
A class D amplifier is provided. The class D amplifier includes an interpolator, a sampling rate converter, a pulse width modulator, a sigma-delta modulator, and a pulse width modulation (PWM) pulse generator (PPG). The sampling rate converter interpolates the output of the interpolator such that the sampling rate converter up-samples the interpolator output by a factor that is greater than one and less than two. The pulse width modulator outputs a multi-bit digital signal. The sigma-delta modulator performs sigma-delta modulation on the pulse width modulator output, the order of the sigma-delta modulation is programmable, and the output of the sigma-delta modulator is a multi-bit, digital signal. At least one of the orders to which the sigma-delta modulator can be programmed is greater than two. The PPG provides a pulse signal such that the width of each pulse is based on the value of the sigma-delta modulator output.