Class-D Amplifier Bias Circuit for Pulse Width Distortion Cancellation
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Solution Overview
Problem
Class-D power amplifiers face issues with harmonics exceeding out-of-band spurious emission limits due to mismatched rise and fall times, which are difficult to control with existing filtering methods, especially in RF applications where low-pass filters are costly and inefficient.
Innovation Solution
A circuit and method that includes a bias circuit with averaging circuits and a comparator to generate a bias voltage signal, balancing the rise and fall times of the output signal to maintain a 50% duty cycle, using cascode transistors and inverters to adjust the digital output signal, thereby reducing second-order harmonics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If switching-mode amplifiers use fast transition (square wave) to reduce transistor power dissipation, then power efficiency is improved, but high frequency content in harmonics increases causing out-of-band spurious emissions to exceed regulatory limits
Solution Approach 1:
The patent converts the harmful effect of parasitic capacitances (which cause pulse width distortion and even-order harmonics) into a beneficial effect by using the same parasitic capacitances as sensing elements. The circuit measures the voltage across the parasitic capacitances to detect duty cycle deviations, then uses this information to generate compensation signals that cancel the distortion. This transforms the parasitic elements from sources of harm into useful sensing mechanisms.
Solution Approach 2:
The patent implements feedback by continuously monitoring the output signal's duty cycle through averaging circuits that measure the voltage across parasitic capacitances. When duty cycle deviations are detected, the system generates compensation signals that are fed back to the switching nodes to correct the distortion. This closed-loop feedback mechanism dynamically adjusts for pulse width distortion, reducing even-order harmonics while maintaining the benefits of fast switching.
2Power
If class-D amplifier uses inverting amplifier stages with parasitic capacitances, then amplification is achieved, but rise and fall time mismatch occurs causing pulse width distortion and even-order harmonics
Solution Approach 1:
The patent introduces intermediary elements (averaging circuits and compensation networks) that mediate between the parasitic capacitances and the output signal. The averaging circuits act as intermediaries to smooth and measure the voltage across parasitic capacitances, extracting duty cycle information. Compensation networks serve as intermediaries to generate corrective signals that counteract the pulse width distortion caused by rise/fall time mismatch, thereby preserving duty cycle accuracy while maintaining amplification.
Solution Approach 2:
The patent changes parameters by dynamically adjusting the compensation signals based on measured duty cycle deviations. The system varies the compensation voltage or current parameters in response to detected rise/fall time mismatches, thereby correcting the output waveform's duty cycle. This parameter adjustment allows the amplifier to maintain accurate duty cycle despite variations in parasitic capacitance effects across different operating conditions.
Data Source
Figure 1A~1B
Figure 1C~1D
Figure 2A~2C
AI summary
A switching-mode power amplifier includes a driver circuit having an input for receiving a radio frequency (RF) signal, an output for outputting a digital output signal, and a bias port for receiving a bias signal, and a bias circuit having a first input coupled to the output of the driver circuit for receiving the digital output signal, a second input coupled to the input of the driver circuit for receiving the RF signal, and an output coupled to the bias port of the driver circuit for providing the bias signal to the driver circuit.