Class D DAC Feedback Loop for Low-Distortion Digital Input
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current digital-to-analog (DAC) converters face issues such as performance degradation due to unmatched rise/fall times, clock jitter limitations, intersymbol interference, and high harmonic distortion, especially at high data rates, and require complex noise filtering to mitigate these problems.
Innovation Solution
A system and method incorporating an interpolation filter to up-sample digital signals, a noise shaping modulator to suppress quantization errors, and a hybrid finite impulse response (FIR) filter/DAC coupled with a Class D delta-sigma pulse width modulation control loop, which includes a Digital Pulse Width Modulation (DPWM) Noise Shaper to spectrally shape noise out of the band of interest, thereby improving conversion accuracy and reducing distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If continuous time DAC implementation is used, then conversion speed is improved, but distortion and in-band noise increase due to unmatched rise/fall times and intersymbol interference
Solution Approach 1:
The patent segments the continuous time conversion process into discrete time slots using an interpolation filter that up-samples the digital signal. This segmentation allows precise control of rise and fall times for each segment, preventing the distortion and intersymbol interference that occur in continuous time implementations while maintaining high conversion speed.
Solution Approach 2:
The patent applies preliminary action by pre-shaping the digital signal through an interpolation filter before conversion. This filter pre-establishes the correct rise and fall time characteristics and timing alignment, preventing distortion and intersymbol interference before they can occur during the conversion process.
2Device complexity
If multi-bit truncation DAC is used, then device complexity is reduced, but static nonlinearity conversion errors increase requiring Dynamic Element Matching schemes
Solution Approach 1:
The patent applies feedback by using a noise shaper that monitors and compensates for quantization errors in real-time. The noise shaper feeds back correction signals to cancel out the static nonlinearity errors introduced by multi-bit truncation, eliminating the need for complex Dynamic Element Matching schemes while maintaining high conversion precision.
3Measurement precision
If discrete time DAC with switched capacitors is used, then conversion accuracy is improved, but circuit area increases due to large charge transfer capacitors
Solution Approach 1:
The patent changes the operating parameters by using an interpolation filter that up-samples the digital signal before conversion. This parameter change allows the use of smaller capacitors in the switched capacitor circuit while maintaining high conversion accuracy, as the up-sampled signal provides more resolution points and reduces the charge transfer requirements.
4Reliability
If continuous time DAC is used, then clock jitter sensitivity increases, but noise filters can mitigate this sensitivity
Solution Approach 1:
The patent segments the conversion process into discrete time intervals with synchronized switching, eliminating the continuous time operation that causes jitter sensitivity. This segmentation approach inherently reduces clock jitter impact without requiring additional noise filtering complexity.
Data Source
AI summary
A system and method is disclosed for a digital to analog converter which includes an interpolation filter to up-sample a digital signal, a noise shaping modulator to suppress in-band quantization errors due to digital pulse width modulation and truncation errors, and a hybrid finite impulse response filter/digital to analog converter coupled to a Class D delta-sigma pulse width modulation control loop.