Class-D Amplifier Dead-Time Compensation for Pulse Width Linearity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing Class-D amplifiers face challenges in reducing non-linearity caused by dead time and reverse recovery time, leading to inefficiencies and distortion, particularly in self-oscillating systems, where prior solutions either complicate the system or fail to provide adequate time resolution and compensation for both rising and falling transitions.
Innovation Solution
A method and device for dead-time compensation in Class-D amplifiers that measure and compensate the delay of both rising and falling level transitions by adding the function of the immediately previous transition delay, ensuring correct pulse widths and linearity, especially in high-power amplifiers with large dead-time, without increasing switching periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dead time is increased to avoid shoot-through, then reliability is improved, but manufacturing precision deteriorates due to non-linearity and distortion
Solution Approach 1:
The patent applies preliminary action by measuring the dead time delay before the power stage switching and using this measurement to pre-compensate the PWM signal. The delay measurement is performed in advance, and the compensated signal is generated before the actual switching occurs, thereby correcting the non-linearity caused by dead time while maintaining the necessary safety interval
Solution Approach 2:
The patent implements feedback by measuring the actual dead time delay through time-to-digital converters that detect the switching node transitions, and using this measured delay information to adjust and compensate the PWM signal. The system continuously monitors the delay and applies real-time compensation to maintain output linearity
2Manufacturing precision
If digital prediction is used to correct delay variation, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent replaces complex digital prediction algorithms with a direct time measurement approach using time-to-digital converters. Instead of using complex digital signal processing to predict and correct delays, the system directly measures the actual delay time and applies simple temporal compensation to the PWM signal, thereby reducing computational complexity while maintaining correction accuracy
Solution Approach 2:
The patent creates a simplified model of the delay characteristics by directly measuring the actual delay time through dedicated time measurement circuits. Rather than using complex digital models or predictions, the system copies the actual delay behavior through direct measurement and applies this measured delay information for compensation
3Manufacturing precision
If dead time compensation is implemented, then manufacturing precision is improved, but loss of time increases due to measurement and compensation overhead
Solution Approach 1:
The patent merges the dead time measurement and compensation functions into the existing driver block and control logic. The time-to-digital converters are integrated with the PWM generation circuitry, and the compensation is applied within the existing control loop, thereby minimizing additional time overhead by combining multiple functions into unified circuit blocks
4Measurement precision
If time-to-digital converters are used to measure delay, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The time-to-digital converters are designed to automatically measure the dead time delay without requiring external control or complex measurement sequences. The converters self-trigger based on the switching node transitions and automatically generate the delay measurement, thereby achieving high measurement precision while minimizing control complexity through self-service operation
Data Source
Figure 1
Figure 2
Figure 3
AI summary
The invention relates to a compensator device for compensating signal dependent delay variations, including dead time and reverse recovery time, causing un-linearity in a Class-D amplifier where the compensator device comprises: a first input terminal for receiving an input pulse width modulated input PWM signal comprising pulses with falling flanks corresponding to a falling level transition and rising flanks corresponding to a rising level transition; and a second input terminal configured to receive the signal provided at an output switching node of a Class-D amplifier; an output terminal for providing a compensated output signal; and controllable delay means configured to receive and delay the pulse modulated input signal, thereby providing a delayed version of the input signal to said output terminal of the compensator device. The compensator device further comprises time measuring means configured for measuring the time between a transition of the signal provided at the output terminal of the compensator device and the corresponding transition of the signal at the output switching node of a Class- D amplifier and based on these measurements providing a control signal to the controllable delay means. An advantageous effect of the present invention is that the rising and falling level transition delays will be substantially similar thus substantially removing non-linearity and obtaining substantially correct pulse widths. The invention further relates to a corresponding method, a driver device and a Class-D amplifier.