Class-D Driver Delay-Line Slew Rate Control for Clean Switching
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Solution Overview
Problem
Class-D amplifiers face challenges in achieving optimal slew rate during switching, which can lead to overshoot or undershoot, degrading power efficiency and requiring careful control to maintain high efficiency.
Innovation Solution
The implementation of a class-D amplifier with a drive circuit that generates control signals for p-type and n-type output transistors, utilizing a multi-bit delay line circuit, current digital-to-analog converters, and transistors to control the slew rate by gradually turning on and off the transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the output transistors are switched rapidly to improve efficiency, then power efficiency is improved, but overshoot or undershoot occurs degrading performance
Solution Approach 1:
The patent applies preliminary action by gradually turning on the complementary transistor before the main output transistor switches state. Specifically, when the first output transistor is turning off, the second output transistor is gradually turned on in advance, and vice versa. This preliminary action ensures that there is always a path for current flow during transitions, preventing overshoot and undershoot while maintaining high efficiency switching operation.
2Reliability
If the transistors are switched slowly to avoid overshoot or undershoot, then output signal accuracy is improved, but power efficiency decreases
Solution Approach 1:
The patent applies dynamics by using different switching speeds for different transistors during the same switching event. The main output transistor switches rapidly for high efficiency, while the complementary transistor switches gradually to prevent overshoot. This dynamic differential switching strategy allows the system to achieve both high efficiency and accurate output signaling by optimizing the switching speed of each transistor based on its specific function.
3Device complexity
If simple switching control is used to reduce complexity, then device complexity is reduced, but slew rate control and overshoot prevention become difficult
Solution Approach 1:
The patent introduces an intermediate control mechanism using a complementary transistor that acts as a mediator between the input signal and the main output transistor. This intermediary transistor is controlled by a delayed version of the input signal and provides gradual current transition during switching events. The intermediary approach enables sophisticated slew rate control without requiring complex control circuits, as the complementary transistor naturally provides the needed current modulation through its gradual switching characteristic.
Data Source
AI summary
A class-D amplifier includes: a p-type output transistor; an n-type output transistor connected in series with the p-type output transistor; and a drive circuit connected to a gate of the p-type output transistor and a gate of the n-type output transistor. The drive circuit receives an input signal, generates a p-type output transistor control signal applied to the gate of the p-type output transistor, and generates an n-type output transistor control signal applied to the gate of the n-type output transistor. When the input signal becomes logic high, the n-type output transistor control signal becomes logic low fast, while the p-type output transistor control signal becomes logic low gradually. When the input signal becomes logic low, the p-type output transistor control signal becomes logic high fast, while the n-type output transistor control signal becomes logic high gradually.