Single-Ended Class D Amplifier With Differential PWM Jitter Cancellation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional class D amplifiers driving stereo headphones with one terminal grounded face performance degradation due to operating clock jitter, requiring expensive crystal resonators and stringent PLL circuit performance, which increases power consumption and costs.

Innovation Solution

A class D amplifier configuration that differentializes PWM outputs using two inductors instead of a transformer, canceling out clock jitter and achieving single-end output without expensive components like crystal resonators, while allowing for reduced clock frequency and improved SN ratio.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional class D amplifier configuration is used to drive stereo headphones with one terminal grounded, then the amplifier can operate with simple connectivity, but performance degrades due to operating clock jitter requiring expensive crystal resonators

Engineering Contradiction:
Improveperformance stabilityVSAvoidcost and complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent converts the harmful effect of clock jitter into a beneficial outcome by differentializing the PWM outputs. The jitter affecting both channels equally is transformed into a common-mode signal that is rejected by the differential configuration, turning the previously harmful jitter into an advantage where the noise cancels itself out in the differential output.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The patent introduces asymmetry in the output configuration by using a differential output structure where the two channels are processed differently before combining. The PWM outputs are inverted for one channel and then combined through capacitors, creating an asymmetric processing path that ultimately produces a single-ended output suitable for headphones while maintaining jitter rejection.

Inventive Principle:
Principle #4Asymmetry

2Reliability

If crystal resonators and stringent PLL circuit performance are used to reduce clock jitter, then operating clock jitter is suppressed, but power consumption increases

Engineering Contradiction:
Improveclock stabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

Instead of using expensive and power-consuming crystal resonators to suppress jitter, the patent accepts the jitter and converts it into a common-mode signal through differential output. The jitter is not eliminated but transformed into a form that is rejected by the differential configuration, significantly reducing power consumption while maintaining performance.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The patent extracts the jitter component from the signal path by using differential output. The jitter is separated as a common-mode signal that appears equally on both channels, allowing it to be rejected by the differential configuration and extracted from the useful audio signal.

Inventive Principle:
Principle #2Taking out (Extraction)

3Manufacturing precision

If high clock frequency is used for PWM modulation, then modulation performance is improved, but power consumption increases

Engineering Contradiction:
Improvemodulation precisionVSAvoidpower consumption
Core Design Contradiction:
Manufacturing precisionVSUse of energy by moving object

Solution Approach 1:

The patent uses partial action by implementing PWM modulation only on one channel while the other channel is inverted and combined through capacitors. This partial modulation approach, combined with the differential configuration, achieves good modulation performance while allowing the use of lower clock frequencies, thereby reducing power consumption.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent merges the two PWM channels through capacitive combining after one channel is inverted. This merging process allows the use of lower clock frequencies because the combination of the two channels achieves the desired modulation performance that would otherwise require higher frequencies in a single-channel system.

Inventive Principle:
Principle #5Merging (Combining)

4Ease of operation

If transformer is used to combine PWM outputs, then output combining is achieved, but device complexity and cost increase

Engineering Contradiction:
Improveoutput combining capabilityVSAvoidcomponent count and complexity
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The patent extracts the combining function from the traditional transformer-based approach and implements it through simple capacitors. The capacitors perform the voltage combining function that would otherwise require a transformer, significantly reducing component count and complexity while maintaining the output combining capability.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent replaces the expensive and complex transformer with cheap capacitors that perform the same combining function. The capacitors are simple, inexpensive components that achieve the voltage combining effect without the complexity and cost of a transformer, making the overall system more cost-effective.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Data Source

PatentUS7800444B2Class D amplifier
Publication Date: 2010.09.21 PANASONIC HOLDINGS CORP
  • US7800444B2 patent drawing
  • US7800444B2 patent drawing
  • US7800444B2 patent drawing

AI summary

A single-end-output class D amplifier handles a load, such as stereo headphones, without using an expensive part such as a crystal resonator or transformer. The class D amplifier is equipped with PWM (Pulse Width Modulation) circuits that perform pulse width modulation of an input signal and output two opposite-phase PWM outputs, PWM output buffers that amplify differential outputs of PWM circuits using a power supply voltage, and inductors that combine PWM outputs amplified by the PWM output buffers.