Class-D Amplifier Loop Filter With Active-RC and Gm-C Integrators

The loop filter is segmented into multiple integrator stages (first integrator, second integrator, third integrator) with distinct functions. Each integrator processes signals at different levels, distributing the computational burden and reducing the power consumption of individual stages while maintaining overall system stability.

Different integrator stages use different architectures optimized for their specific functions. The first integrator uses a pseudo-differential architecture for accurate summation, while subsequent integrators use simplified structures for efficient processing, allowing each part to operate optimally with minimal power consumption.

The pseudo-differential integrator stage is segmented into separate positive and negative signal paths, with dedicated summation nodes for each polarity. This segmentation allows accurate summation while isolating noise sources to specific paths, reducing overall noise contribution.

Virtual ground nodes are introduced as intermediaries in the integrator circuits. These virtual grounds provide stable reference points for signal summation without requiring physical ground connections, reducing offset errors and noise while maintaining summation accuracy.

Feedforward summation operations are performed preliminarily at intermediate stages rather than waiting for final integration. The first integrator performs feedforward summation of input and feedback signals before subsequent integration stages, improving loop response while distributing power consumption across multiple stages.

The architecture uses parameter optimization in the feedforward paths, including transconductance values and capacitor sizes, to achieve the required loop response with minimal power consumption. Transistor sizing and bias currents are carefully selected to balance performance and power efficiency.