Class-D Power Amplifier Mid-Voltage Control for Harmonic Suppression
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Solution Overview
Problem
Near Field Communication (NFC) devices using push pull class D power amplifiers face significant power losses and reduced efficiency due to the need for high-quality electromagnetic compatibility (EMC) filters to suppress unwanted higher harmonics, which are also large and expensive.
Innovation Solution
A power amplifier with a mid-voltage control circuit that temporarily holds output voltages at a mid-voltage level between VDD and VSS, reducing higher order harmonics and thereby reducing the demand on secondary filters like EMC filters, allowing for adaptive harmonic suppression and improved system efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If high-quality EMC filters are used to suppress higher harmonics, then electromagnetic compatibility is improved, but power losses increase and system efficiency decreases
Solution Approach 1:
The patent applies preliminary action by modifying the PWM signal before it reaches the power amplifier. Specifically, the signal is adjusted during the transition periods between high and low states to include a mid-voltage level, which proactively suppresses harmonics generation at the source rather than requiring post-processing filtration
Solution Approach 2:
The patent converts the potentially harmful square wave output with high harmonics into a beneficial waveform by introducing mid-voltage transitions. This transformation maintains the efficiency benefits of class-D amplification while inherently suppressing harmonics, turning what would be a harmful characteristic into a beneficial one
2Object-affected harmful factors
If high-quality EMC filters are used to suppress higher harmonics, then electromagnetic compatibility is improved, but device size and cost increase
Solution Approach 1:
The patent applies preliminary action by modifying the PWM signal before it reaches the power amplifier. Specifically, the signal is adjusted during the transition periods between high and low states to include a mid-voltage level, which proactively suppresses harmonics generation at the source rather than requiring post-processing filtration
Solution Approach 2:
The patent extracts the harmonic suppression function from the traditional EMC filter and relocates it to the control circuitry. By implementing mid-voltage control in the PWM generation stage, the patent removes the need for complex external filtering components, effectively taking out the filtration requirement from the system
3Object-affected harmful factors
If alternative power amplifier types are used to avoid higher harmonics, then electromagnetic compatibility is improved, but efficiency decreases below that of push pull class D with EMC filter
Solution Approach 1:
The patent applies dynamics by making the power amplifier output waveform dynamic rather than static. Instead of using a fixed alternative amplifier topology, the patent dynamically adjusts the voltage level during transition periods by introducing mid-voltage states, allowing the system to maintain class-D efficiency while adaptively suppressing harmonics
Solution Approach 2:
The patent changes the voltage parameter during signal transitions by introducing a mid-voltage level between the high and low states. This parameter modification occurs specifically during transition periods, altering the waveform characteristics to suppress harmonics while maintaining the overall efficiency of the class-D amplification scheme
Data Source
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AI summary
Embodiments of a power amplifier and method of operating a power amplifier are disclosed. In one embodiment, a power amplifier includes a pulse wave modulation (PWM) controller, a first power control stage configured to drive a first output between VDD and VSS in response to a control signal from the PWM controller, a second power control stage configured to drive a second output between VDD and VSS in response to a control signal from the PWM controller, and a mid-voltage control circuit configured to hold the voltage of the first output at a mid-voltage that is between VDD and VSS during an interval between when the first output is driven between VDD and VSS and hold the voltage of the second output at the mid-voltage during an interval between when the first output is driven between VDD and VSS.