Multi-Level Class D Amplifier Circuitry for Lower Quiescent Power
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Solution Overview
Problem
Class D amplifiers in small form factor devices face challenges in further improving power efficiency, particularly in devices with limited battery capacity, where quiescent power consumption is significant due to voltage developments across resistors in feedback paths when no output is provided to the transducer.
Innovation Solution
Implementing a Class D amplifier circuitry that uses multi-level modulation schemes, such as BD3-BD3 or hybrid BD2-BD3 arrangements, to reduce quiescent power consumption by allowing output signals to take more than two discrete levels, thereby minimizing voltages across feedback resistors during zero transducer input states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If Class D amplifier circuitry uses conventional two-level modulation schemes, then the circuit complexity is low, but quiescent power consumption is high due to voltage developments across feedback resistors
Solution Approach 1:
The patent changes the modulation parameter from two-level to multi-level (three-level or higher) quantization, transforming the discrete signal levels from {0, 1} to {0, 1, 2, ...}. This parameter change directly reduces quiescent power consumption by minimizing voltage across feedback resistors during zero transducer input states, while the additional complexity remains manageable through systematic circuit implementation
2Loss of energy
If Class D amplifier circuitry increases the number of discrete signal levels from N to M (where M > N), then power efficiency is improved, but the device complexity increases
Solution Approach 1:
The patent segments the amplification function into distinct modular blocks: input buffer circuitry, analog modulator circuitry, and quantizer circuitry. Each block performs a specific function with the multi-level modulation, allowing the complexity to be distributed and managed systematically. The segmentation enables independent optimization of each module while achieving overall power efficiency improvements
Solution Approach 2:
The patent implements dynamic signal level selection where the quantizer circuitry adaptively chooses from multiple discrete signal levels (M > N) based on the input signal characteristics. This dynamic approach allows the circuit to optimize power consumption in real-time by selecting appropriate signal levels, improving power efficiency while managing complexity through adaptive control mechanisms
3Use of energy by moving object
If multi-level modulation schemes are implemented, then average power consumption is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent designs the quantizer circuitry to serve multiple functions: it performs multi-level quantization for power efficiency, maintains compatibility with standard digital interfaces, and provides flexible signal level selection. This multi-functionality allows the same circuit block to achieve power savings while maintaining ease of manufacture through standardized design approaches and interfaces
Data Source
AI summary
Class D amplifier circuitry comprising: input buffer circuitry configured to receive a first digital input signal modulated according to a first modulation scheme in which the digital input signal can take a first plurality N of discrete signal levels; analog modulator circuitry configured to generate an analog modulated signal based on an analog output signal output by the input buffer circuitry; and quantizer circuitry configured to generate an output signal based on the analog modulated signal, wherein the output signal is modulated according to a second modulation scheme in which the output signal can take a second plurality M of discrete signal levels, wherein the second plurality M is greater than the first plurality N.