Class D Topology for Rapid Overload Current Regulation
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Solution Overview
Problem
Conventional power supply control circuits face challenges in responding rapidly and effectively to overload current conditions, often leading to component damage or system failures due to slow response times and large circuit sizes.
Innovation Solution
A class D overload current limiter topology is employed, using switches to regulate the power supply output by drawing current off the gate of the power switch, allowing for rapid discharge and control of the power switch, minimizing stress on the FET and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional linear op-amp is used to control current and respond to overcurrent conditions, then the circuit can provide controlled current limiting, but the response time is slow which may result in excessive current flow and component damage
Solution Approach 1:
The patent replaces the linear op-amp (analog continuous control system) with a class D switching regulator topology that uses pulse-width modulation (PWM) and switching elements. This substitution enables much faster response times because the switching elements can transition between on and off states almost instantaneously, compared to the gradual response of a linear op-amp. The switching topology achieves current limiting through rapid on-off cycles rather than continuous analog control, thereby resolving the contradiction between reliability protection and response speed.
Solution Approach 2:
The patent introduces dynamic switching control where the power switch transitions between fully on and fully off states based on real-time current feedback. The class D topology uses a control switch that dynamically adjusts the duty cycle of the power switch to maintain current within safe limits. This dynamic operation allows the system to respond instantly to overcurrent conditions by rapidly reducing the duty cycle, achieving both fast response time and effective current protection that static or slowly responding circuits cannot provide.
2Speed
If a fast comparator and latch circuit are used to rapidly shut down the power switch upon detecting overcurrent, then the response time is fast, but the circuit complexity increases and may cause power oscillation when system noise causes the current overload detector to trip
Solution Approach 1:
The patent integrates multiple functions into the class D switching regulator control circuitry. The same control switch and PWM controller that regulate normal operation also detect and respond to overcurrent conditions. The current sense amplifier and PWM controller serve dual purposes: regulating current during normal operation and detecting/shutting down during overcurrent events. This multi-functionality eliminates the need for separate fast comparator and latch circuits, achieving fast protection response without increasing overall circuit complexity.
Solution Approach 2:
The patent employs continuous feedback through the current sense amplifier that monitors the current through the power switch and feeds this information back to the PWM controller. This feedback mechanism provides inherent noise filtering and hysteresis effects that prevent false triggering from transient noise spikes. The feedback loop naturally dampens oscillations and provides stable operation, eliminating the need for complex latch circuits while maintaining fast response through the high-bandwidth feedback path.
3Reliability
If a linear op-amp is used to control the power switch, then the circuit can provide stable current control, but the chip area required is large to achieve high bandwidth and low impedance gate drive
Solution Approach 1:
The patent replaces the linear op-amp with a switching-based class D regulator topology that uses a PWM controller and switching elements. This substitution dramatically reduces chip area because switching elements (MOSFETs, diodes) and simple control logic occupy far less space than the large operational amplifier circuits required for high-bandwidth linear control. The switching topology achieves equivalent or superior current control stability through high-frequency PWM modulation and feedback, eliminating the need for large chip area while maintaining reliable current control.
4Reliability
If the power switch is rapidly shut down using a latch circuit upon detecting overcurrent, then the protection response is fast, but the load is completely powered off which may not be desirable for all applications
Solution Approach 1:
The patent uses periodic PWM switching to control the power switch rather than a latching off-state. When overcurrent is detected, the PWM controller reduces the duty cycle of the power switch to a safe level rather than completely shutting it off. This periodic on-off action at high frequency maintains a controlled amount of power to the load while preventing excessive current. The load receives reduced but continuous power during overcurrent conditions, providing protection while maintaining operational functionality, unlike complete shutdown approaches.
Solution Approach 2:
The patent implements dynamic current control where the power switch duty cycle is continuously adjusted based on real-time current feedback. During overcurrent conditions, the duty cycle is dynamically reduced to maintain current at a safe threshold rather than completely shutting off the switch. This dynamic adjustment allows the system to provide protection while maintaining partial power delivery to the load, enabling the load to continue operating at reduced capacity rather than being completely powered off. The control switch and PWM controller enable this dynamic response that balances protection with continuous power availability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a rapid and efficient response to overcurrent conditions, minimizing disruptions to the power supply and extending the longevity of the power supply output FET, while maintaining a constant current level to the load, thus improving power supply performance and reducing costs.
Implementation Method 1
A capacitor Cgate is coupled to the gate of pass FET 15 to contribute to maintaining a gate voltage for enhanced operation of pass FET 15
Data Source
AI summary
A system and method for responding to a current overload condition in a power switch provides a class D topology that applies a current sink or current source to the gate of the power switch. The current sink or source decreases or increases current flowing through the power switch to regulate power switch output current in the event of an overload. A timer for current regulation can be provided to shut off the power switch if the overload condition persists. A set of differently rated switches can be used separately or together to provide a range of current regulation response, from a wide regulation range with a fast response, to a narrow regulation range with a slow response. The system provides a rapid response to an overload condition and output current regulation without disabling the power switch to overcome short term overloads.