Class D Power Output Stage With Low-Voltage Switching Transistors
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Solution Overview
Problem
Conventional class D power stages for ×DSL applications face challenges with high power dissipation and area requirements due to high supply voltages and large transistor dimensions, which are exacerbated by high switching frequencies and the need for high-voltage transistors with thick gate oxides and long channel lengths.
Innovation Solution
A class D power output stage design using low-voltage switching transistors with complementary high-voltage limiting transistors, along with a level matching device to generate control signals, reduces power dissipation and area requirements by allowing efficient switching with lower voltage swings and smaller transistor dimensions, and incorporates clamping transistors to prevent excessive voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If high-voltage transistors with thick gate oxide and long channel lengths are used to withstand supply voltage, then electrical strength is improved, but area and power dissipation increase due to large width-to-length ratio requirements
Solution Approach 1:
The power stage is divided into multiple controllable paths with transistors operating at different voltage levels. Each transistor is sized appropriately for its specific voltage requirement rather than all transistors being oversized for the maximum supply voltage, reducing total area while maintaining electrical strength.
Solution Approach 2:
Different transistors in the circuit are designed with different electrical characteristics matched to their local requirements. Transistors operating at lower voltages use smaller dimensions and thinner gate oxides, while only the necessary transistors handle the full supply voltage, optimizing the trade-off between electrical strength and area.
2Reliability
If large width-to-length ratio is selected to achieve low channel resistance, then conductivity is improved, but gate-source capacitance increases proportionally to gate area
Solution Approach 1:
The current path is segmented into multiple transistor stages. The first transistor handles the full supply voltage with moderate dimensions, while subsequent transistors operate at lower voltages with smaller dimensions, collectively achieving low channel resistance without proportionally large gate capacitance.
Solution Approach 2:
The voltage operating point is changed for different transistors in the signal path. By operating transistors at different voltage levels rather than all at the maximum supply voltage, the patent reduces gate-source capacitance and associated power dissipation while maintaining adequate channel conductivity.
3Strength
If thick gate oxide and long channel lengths are used for high voltage capability, then electrical strength is improved, but switching speed decreases due to increased capacitance
Solution Approach 1:
The switching operation is segmented into multiple stages with transistors operating at different voltage levels. Lower-voltage transistors switch faster due to reduced capacitance, and the multi-stage architecture ensures the overall system achieves both high voltage capability and fast switching.
Solution Approach 2:
The patent changes the operating voltage parameter for different transistors in the path. Transistors operating at lower voltages exhibit faster switching speeds due to lower gate capacitance, while the series combination maintains the required high voltage capability, resolving the speed-strength trade-off.
4Productivity
If drive voltages of VDD/2 are used for gate terminals to operate transistors efficiently as switches, then switching efficiency is improved, but driver stage complexity and area increase
Solution Approach 1:
The patent changes the gate drive voltage parameter from the conventional VDD/2 to full-rail voltages (VDD or VSS). This allows the use of simpler driver stages that directly output the supply voltages, reducing driver complexity while maintaining efficient switching through proper timing control of the complementary signals.
Data Source
AI summary
A class D power output stage for switching a supply voltage comprises a limiting transistor with a controllable path and a control terminal, a complementary limiting transistor with a controllable path and a control terminal, a switching transistor with a controllable path and a control terminal, and a complementary switching transistor with a controllable path and a control terminal. A switched output signal between the controllable paths of the limiting and complementary limiting transistors can be taped off, the controllable paths of the limiting and the complementary limiting transistors are connected together and are connected to a first and a second supply terminal via the controllable paths of the switching and complementary switching transistors, and the switching and the complementary switching transistors have a lower electrical strength than the limiting and complementary limiting transistors. The output stage further comprises a level matching device for generating control signals in response to an input switching signal. The matching device is connected to the supply voltage and the control signals are fed to the control terminals.