Class-D Amplifier Pre-Driver Calibration for Slew Rate Control

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Solution Overview

Problem

Class-D amplifiers face challenges in maintaining optimal slew rate during switching, which can lead to over-shoot and under-shoot, degrading power efficiency.

Innovation Solution

The implementation of an auto-calibration control system for class-D amplifier driver circuits, which includes a PWM signal generator, pre-driver circuits with slew rate and bias voltage controllers, and an output monitor to detect duty cycles and adjust gate voltages accordingly.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If class-D amplifiers use rail-to-rail output switching with transistors operating as binary switches, then power efficiency is improved and heat dissipation is minimized, but slew rate control becomes difficult leading to over-shoot and under-shoot

Engineering Contradiction:
Improvepower efficiencyVSAvoidslew rate control
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The pre-driver circuit adjusts the gate voltage of the output transistor before the actual switching operation occurs. By calibrating the gate voltage in advance based on the duty cycle, the transistor is prepared for optimal switching performance, preventing over-shoot and under-shoot while maintaining the binary switch operation for high efficiency.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system monitors the actual duty cycle of the output signal and uses this feedback to adjust the gate voltage through the pre-driver circuit. This closed-loop control ensures that the slew rate is optimized based on real-time operating conditions, maintaining reliable switching performance while preserving power efficiency.

Inventive Principle:
Principle #23Feedback

2Reliability

If the gate voltage is adjusted to improve slew rate, then switching performance is improved, but power efficiency decreases due to increased power dissipation

Engineering Contradiction:
Improveswitching performanceVSAvoidpower dissipation
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The pre-driver circuit applies only the necessary gate voltage adjustment required for proper switching, not excessive voltage. By calibrating to the precise threshold needed for optimal slew rate, the system achieves adequate switching performance without the additional power dissipation that would result from over-driving the transistor.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The system dynamically adjusts the gate voltage parameter based on the duty cycle. By changing this electrical parameter adaptively, the system optimizes switching performance for each operating condition while minimizing power dissipation, avoiding fixed high-voltage gate drive that would cause excessive power loss.

Inventive Principle:
Principle #35Parameter changes

3Device complexity

If a fixed gate voltage is used to simplify the driver circuit, then device complexity is reduced, but over-shoot and under-shoot occur degrading performance

Engineering Contradiction:
Improvedriver circuit complexityVSAvoidoutput signal accuracy
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The pre-driver circuit serves as an intermediary between the simple binary switch and the control system. It provides the necessary gate voltage calibration function without requiring complex control logic in the main amplifier, thus maintaining overall circuit simplicity while enabling accurate duty cycle control to prevent over-shoot and under-shoot.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20250202444A1Auto-calibration driving strength system for class-d amplifier
Publication Date: 2025.06.19 NUVOTON
  • US20250202444A1 patent drawing
  • US20250202444A1 patent drawing
  • US20250202444A1 patent drawing

AI summary

A class-D amplifier includes a pulse width modulation (PWM) signal generator configured to generate an input signal, a p-type output transistor and an n-type output transistor connected in series with the p-type output transistor at an output terminal, and an output monitor connected to the output terminal and configured to detect a duty cycle of an output signal at the output terminal. The amplifier includes a pre-driver circuit having a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal is connected to the PWM signal generator to receive the input signal, the second input terminal is connected to the output monitor to receive the duty cycle, the first output terminal is connected to a gate of the p-type output transistor, and the second output terminal is connected to a gate of the n-type output transistor.