Multi-Channel Class-D Amplifier Synchronization for Beat Frequency Control
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Solution Overview
Problem
Multi-channel class-D amplifiers experience undesired beat frequencies due to frequency differences between switching frequencies of individual channels, leading to audible noise and high peak power consumption, which is problematic in audio and other applications.
Innovation Solution
Implementing synchronization signals and multi-phase clocks to synchronize switching frequencies across channels, ensuring they are slightly offset in time, thereby reducing beat frequencies and spreading power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If multiple class-D amplifiers are placed in close proximity to achieve space efficiency, then space utilization is improved, but beat frequencies are generated due to frequency differences between channels
Solution Approach 1:
The patent applies periodic action by using a single shared clock signal that periodically synchronizes all amplifier channels. The clock signal operates at a fixed frequency (e.g., 384 kHz) and periodically resets the phase counters in each channel, ensuring that all channels switch at the same frequency and remain coherent with each other, thereby eliminating beat frequencies while allowing close physical placement of amplifiers
Solution Approach 2:
The patent implements universality by using a single shared clock signal that serves all amplifier channels simultaneously. Instead of each channel having its own independent clock, one universal clock signal performs the time-base function for all channels, coordinating their switching operations and ensuring frequency coherence across the entire multi-channel amplifier system
2Productivity
If all channels process signals simultaneously to maximize productivity, then processing throughput is improved, but peak power consumption increases
Solution Approach 1:
The patent uses periodic action with phase counters that increment through multiple states (e.g., four phases) before resetting. This causes channels to be enabled periodically in a staggered sequence rather than all at once, spreading the power consumption over time while maintaining continuous signal processing capability across all channels
Solution Approach 2:
The patent applies segmentation by dividing the processing of each channel into multiple phase segments (e.g., four phases per channel). Each phase corresponds to a specific time window during which a subset of channels is enabled. This segmentation allows the system to maintain high productivity by continuously processing signals across different phases while reducing peak power by enabling only one phase worth of channels at any given moment
3Device complexity
If independent oscillators are used in each channel to simplify design, then device complexity is reduced, but frequency mismatches occur causing beat frequencies
Solution Approach 1:
The patent extracts the oscillation function from individual channels and consolidates it into a single shared clock signal source. Instead of each channel containing its own oscillator circuitry, the oscillation function is taken out and centralized, with the single clock signal distributed to all channels to provide the time base for switching operations
Solution Approach 2:
The patent introduces a shared clock signal as an intermediary between the control logic and the amplifier channels. This intermediary clock signal mediates the timing and switching operations of all channels, ensuring they operate at the same frequency and remain synchronized, thereby preventing frequency mismatches without requiring complex coordination between independent oscillators
Data Source
AI summary
Various embodiments are described herein for a multi-channel class-D amplifier and an associated processing method. In general, the multi-channel class-D amplifier comprises a signal source that provides a plurality of input signals and generates synchronization information; and a plurality of class-D amplifier channel modules, each class-D amplifier channel module being configured to process a corresponding input signal from the plurality of input signals according to the synchronization information to produce an output signal. The switching frequencies employed by the plurality of class-D amplifier channel modules are substantially similar to one another and the processing of the plurality of input signals is offset in time across the plurality of class-D amplifier channel modules.