Class-F Power Amplifier Harmonic Network for High-Frequency Efficiency
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Solution Overview
Problem
Existing class-F amplifiers face challenges in achieving high efficiency at high frequencies due to increased enclosure area and output capacity of FETs, particularly when using distributed constant circuits or downsized lumped constant circuits, which are not applicable to high-power internally matched FETs with dc bias from RF output terminals.
Innovation Solution
A class-F amplifier design incorporating a first reactance circuit that is open for dc and shorted for even harmonics, and a second reactance circuit that is shorted for dc and open for odd harmonics, with a fundamental matching circuit that includes a choke coil and dc cutting capacitor, allowing for downsizing and efficient operation even at high frequencies where the output capacity of FET is significant.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a distributed constant circuit is used as a harmonic processor in an internally matched FET amplifier, then class-F operation with enhanced efficiency is achieved, but the enclosure area increases
Solution Approach 1:
The patent transforms the harmonic processor from a distributed constant circuit to a lumped constant circuit configuration. This parameter change in circuit topology allows the same class-F operation principles to be applied while significantly reducing the physical enclosure area required for implementation.
Solution Approach 2:
Instead of using the conventional distributed constant circuit approach for harmonic processing, the patent inverts the design philosophy by employing a lumped constant circuit with reversed connection topology - connecting the harmonic processor between the drain and RF output terminal rather than using the traditional distributed structure, thereby achieving area reduction while maintaining class-F functionality.
2Area of stationary object
If a downsized lumped constant circuit is used as a harmonic processor, then enclosure area is reduced, but the circuit becomes inapplicable to high power internally matched FETs with dc bias from RF output terminals
Solution Approach 1:
The patent designs the lumped constant circuit harmonic processor to serve multiple functions simultaneously: it processes harmonics for class-F operation, handles high power levels, and accommodates the dc bias configuration of internally matched FETs. The circuit is configured to be open for dc and odd harmonics while providing the necessary impedance transformations, making it universally applicable to high power internally matched FET amplifiers.
Solution Approach 2:
The patent applies different impedance characteristics to different frequency components at specific circuit locations. The harmonic processor is designed with local quality variations - being open for dc and odd harmonics while providing specific impedance transformations for even harmonics and the fundamental frequency, enabling it to handle high power internally matched FET configurations effectively.
3Loss of energy
If conventional harmonic processors are used, then class-F operation is achieved at frequencies where FET output capacity is negligible, but efficiency deteriorates at high frequencies where output capacity is significant
Solution Approach 1:
The patent modifies the circuit parameters and topology to account for significant FET output capacity at high frequencies. The lumped constant circuit is designed with specific element values and connections that compensate for the capacitive effects of the FET output, maintaining class-F operation and efficiency even when the output capacity is no longer negligible.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables high-efficiency class-F operation at high frequencies by optimizing the impedance matching and reactance configurations, reducing the size of the harmonic processor, and maintaining efficiency even when the output capacity of the FET is non-negligible.
Implementation Method 1
the first reactance circuit is configured to be open for a dc component, shorted for components of angular frequencies 2ωo, 4ωo, . . . , 2nωo
Implementation Method 2
the second reactance circuit is configured to be shorted for a dc component, and open for components of angular frequencies 3ωo, 5ωo, . . . , (2n+1)ωo
Implementation Method 3
parallel resonant with the output capacitor of the amplifying element for components of angular frequencies 3ωo, 5ωo, . . . , (2n+1)ωo
Implementation Method 4
a fundamental matching circuit disposed at an output terminal end of the amplifying element
Data Source
AI summary
An FET outputs a signal including a component of angular frequency ωo of input signal and harmonic components, a first two-terminal reactance circuit interconnects an output terminal and a ground terminal of the FET, a fundamental matching circuit is connected to an output terminal end of the FET, a second two-terminal reactance circuit is connected between an input terminal of the matching circuit and the output terminal, the FET has a parallel circuit of an output resistor and an output capacitor, the first two-terminal reactance circuit is open for a dc, shorted for angular frequencies 2ωo, 4ωo, . . . , 2nωo, and parallel resonant with the output capacitor for angular frequencies 3ωo, 5ωo, . . . , (2n+1)ωo, and the second two-terminal reactance circuit is shorted for a dc, and open for angular frequencies 3ωo, 5ωo, . . . , (2n+1)ωo.