Class-F Power Amplifier Harmonic Reactance for High-Frequency FETs
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Solution Overview
Problem
Existing class-F amplifiers face challenges in achieving high efficiency at high frequencies due to increased enclosure area and output capacity issues, particularly when using distributed constant circuits or lumped constant circuits with dc bias, which are not applicable to high-power internally matched FETs.
Innovation Solution
A class-F amplifier design incorporating a first reactance circuit that is open for dc components and shorted for even harmonics, and a second reactance circuit that is shorted for dc components and open for odd harmonics, allowing for a parallel resonant configuration with an output capacitor, enabling efficient operation even at high frequencies where the output capacity of FET is non-negligible.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a distributed constant circuit is used as a harmonic processor in an internally matched FET, then the amplifier can achieve class-F operation with improved efficiency, but the enclosure area increases
Solution Approach 1:
The patent changes the operating parameters by designing reactance circuits with specific impedance characteristics that transform the harmonic processing approach. The first reactance circuit is designed to present specific impedances at even and odd harmonics, enabling class-F operation without requiring a large distributed constant circuit
Solution Approach 2:
The reactance circuits serve multiple functions simultaneously: they process harmonics for efficiency improvement, provide impedance matching for the fundamental wave, and work with the internally matched FET structure. This multi-functionality eliminates the need for separate large-area distributed circuits
2Area of stationary object
If a lumped constant circuit is used as a harmonic processor with direct dc bias, then the circuit area is reduced, but it becomes inapplicable to high power internally matched FETs with dc bias supplied from RF output terminal
Solution Approach 1:
The patent modifies the circuit parameters by designing the reactance circuits to present specific impedance characteristics at different frequencies. The first reactance circuit is configured to be open at DC, shorted at even harmonics, and have specific impedance at odd harmonics, making it compatible with internally matched FET structures while maintaining compact size
Solution Approach 2:
The harmonic processing function is segmented into two separate reactance circuits with distinct functions: the first reactance circuit handles even harmonics and DC blocking, while the second reactance circuit handles odd harmonics. This segmentation enables compact implementation compatible with internally matched FETs
3Reliability
If conventional harmonic processors are used, then class-F operation can be achieved at frequencies where output capacity of FET is negligible, but they fail to work at high frequencies where output capacity of FET is non-negligible
Solution Approach 1:
The patent addresses high-frequency operation by designing reactance circuits with frequency-dependent impedance characteristics that compensate for the non-negligible output capacity of the FET. The circuits are configured to present appropriate impedances at harmonics while accounting for the FET's output capacitance effects at high frequencies
Solution Approach 2:
The reactance circuits act as intermediary elements between the FET output and the load, transforming the impedance seen by the FET at harmonic frequencies. This intermediary transformation enables class-F operation by creating the necessary short-circuit conditions for even harmonics despite the FET's output capacity at high frequencies
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design allows for downsizing and high efficiency in class-F operation at high frequencies by optimizing the reactance circuits and fundamental matching circuits, reducing the bandwidth and area requirements while maintaining impedance matching for fundamental waves.
Implementation Method 1
the first reactance circuit is configured to be open for a dc component, shorted for components of angular frequencies 2ωo, 4ωo,..., 2nωo, where n is an arbitrary integer of 1 or more, and parallel resonant with the output capacitor of the amplifying element for components of angular frequencies 3ωo, 5ωo,..., (2n+1)ωo
Implementation Method 2
the second reactance circuit is configured to be shorted for a dc component, and open for components of angular frequencies 3ωo, 5ωo,..., (2n+1)ωo
Data Source
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AI summary
An FET outputs a signal including a component of angular frequency w o of input signal and harmonic components, a first two-terminal reactance circuit interconnects an output terminal and an earth terminal of the FET, a fundamental matching circuit is connected to an output terminal end of the FET, a second two-terminal reactance circuit is connected between an input terminal of the matching circuit and the output terminal, the FET has a parallel circuit of an output resistor and an output capacitor, the first two-terminal reactance circuit is open for a dc, shorted for angular frequencies 2ωo, 4ωo,..., 2nωo, and parallel resonant with the output capacitor for angular frequencies 3ωo, 5ωo,..., (2n+1)ωo, and the second two-terminal reactance circuit is shorted for a dc, and open for angular frequencies 3ωo, 5ωo,..., (2n+1)ωo.