Class-F Power Amplifier Circuit for Higher Output With Lower Consumption
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Solution Overview
Problem
Power amplifier circuits in mobile communication devices face challenges in increasing maximum output power and improving power-added efficiency (PAE), with existing solutions not adequately addressing the high power consumption and efficiency requirements.
Innovation Solution
A power amplifier circuit configuration featuring vertically connected transistors, a voltage regulator circuit, and termination/filters that short-circuit or open-circuit specific harmonics to operate in a class-F mode, enhancing power-added efficiency and increasing maximum output power by shaping voltage and current waveforms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If two transistors are vertically connected to increase maximum output power, then the output power is doubled, but the power consumption increases and power-added efficiency deteriorates
Solution Approach 1:
The power amplifier is divided into two separate transistor stages (first transistor and second transistor) connected in series. Each transistor handles a portion of the amplification process, allowing independent optimization of each stage's power consumption while achieving cumulative output power doubling. The first transistor amplifies the input signal and the second transistor further amplifies the output, with each stage consuming less power than a single high-power transistor would require.
Solution Approach 2:
The patent changes the operating parameters of the transistors by introducing specific capacitance values (first capacitance between 0.1pF-10pF, second capacitance between 0.1pF-10pF) and inductance values (first inductance between 0.1nH-10nH, second inductance between 0.1nH-10nH). These parameter adjustments optimize the power consumption and efficiency of each transistor stage while maintaining the doubled output power capability.
2Use of energy by moving object
If harmonics are controlled to enable class-F operation for improved power-added efficiency, then power consumption is reduced, but the circuit complexity increases
Solution Approach 1:
Capacitors and inductors are introduced as intermediary elements to control harmonic frequencies. The first capacitor connects the emitter of the first transistor to ground, the second capacitor connects the emitter of the second transistor to ground, the first inductor connects the collector of the first transistor to the base of the second transistor, and the second inductor connects the collector of the second transistor to the base of the first transistor. These intermediaries enable class-F operation by shaping voltage and current waveforms to reduce power consumption while maintaining manageable circuit complexity.
3Power
If vertically connected transistor configuration is used to double signal amplitude, then output power increases, but the circuit design complexity increases
Solution Approach 1:
The patent merges multiple functions into the vertically connected transistor configuration. The series connection of two transistors simultaneously achieves signal amplitude doubling, power output doubling, and class-F operation capability. The capacitors and inductors integrated into the configuration serve multiple purposes: biasing, harmonic control, and impedance matching, thereby reducing overall design complexity despite the increased power handling capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The configuration effectively doubles the signal amplitude and output power, reduces power consumption, and improves power-added efficiency by operating in a class-F mode, while maintaining efficient power handling and reduced circuit size.
Implementation Method 1
the upper and lower transistors are connected to each other via a capacitor
Implementation Method 2
the emitter of the upper transistor is grounded via an inductor
Implementation Method 3
at least one termination circuit that short-circuits one of an even-order harmonic or an odd-order harmonic of the amplified signal to ground potential
Data Source
AI summary
A power amplifier circuit includes a lower transistor having a first terminal, a second terminal connected to ground, and a third terminal, wherein a first power supply voltage is supplied to the first terminal, and an input signal is supplied to the third terminal; a first capacitor; an upper transistor having a first terminal, a second terminal connected to the first terminal of the lower transistor via the first capacitor, and a third terminal, wherein a second power supply voltage is supplied to the first terminal, an amplified signal is outputted to an output terminal from the first terminal, and a driving voltage is supplied to the third terminal; a first inductor that connects the second terminal of the upper transistor to ground; a voltage regulator circuit; and at least one termination circuit that short-circuits an even-order harmonic or odd-order harmonic of the amplified signal to ground potential.