CLB Logic Cell Layout for Higher LUT Packing and Timing
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Solution Overview
Problem
Current Complex Logic Block (CLB) based Programmable Logic Devices (PLDs) face limitations in flexibility and efficiency for performing logic, register, arithmetic functions, and packing logic functions due to the constraints of existing logic cells.
Innovation Solution
The proposed solution involves CLBs arranged in rows and columns with interconnect lines, each containing a first and second slice of logic cells, where at least one logic cell includes Look Up Tables and an arithmetic logic circuit capable of generating carry signals, and features register feedback and input multiplexing to enable efficient logic operations on different input sets, enhancing logic packing and timing capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional logic cells with same input sets are used, then device complexity is reduced, but logic packing efficiency deteriorates
Solution Approach 1:
The logic cell is segmented into multiple independent LUTs (Look-Up Tables), each capable of receiving different input sets. This segmentation allows each LUT to be optimized for specific logic functions independently, improving packing efficiency without significantly increasing overall device complexity through modular design.
Solution Approach 2:
The logic cell is designed with multi-functional LUTs that can process different input sets simultaneously. Each LUT can be configured to handle various logic functions with different input combinations, making the cell universally applicable to diverse logic packing requirements without requiring separate dedicated cells for each function type.
2Reliability
If register feedback connections are added, then timing capabilities are improved, but device complexity increases
Solution Approach 1:
The register feedback connection merges the output of the logic cell back to its input, creating a compact feedback path within the same cell structure. This integration improves timing capabilities by reducing feedback delay without requiring separate external feedback paths, thereby limiting the increase in device complexity.
Solution Approach 2:
A feedback path is implemented that connects the registered output back to the LUT inputs through a multiplexer. This feedback mechanism enables the cell to maintain state information and improve timing control for sequential logic operations, with the complexity managed through efficient path selection rather than multiple redundant connections.
3Adaptability or versatility
If logic cells are limited to single input set, then ease of manufacture is improved, but flexibility deteriorates
Solution Approach 1:
The logic cell inputs are made dynamic through multiplexer selection, allowing the same physical LUT input pins to be dynamically assigned to different input sets based on the required logic function. This dynamic reconfigurability provides flexibility for various logic operations while maintaining a fixed physical structure that is relatively easy to manufacture.
Solution Approach 2:
The cell's input configuration parameters are made changeable through programmable logic that can select different input sets for each LUT. This allows the same hardware structure to be manufactured once and then configured for different input requirements through programming, achieving flexibility without requiring multiple manufacturing variants.
Data Source
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AI summary
A CLB-based PLD with logic cells having improved logic, register, arithmetic, logic packing and timing functions and capabilities is disclosed. The CLBs of the PLD are arranged in rows and columns of an array and are interconnect by a plurality of interconnect lines. Each of the plurality of CLBs has a first slice of logic cells and a second slice of logic cells arranged in a first column and a second column. First and second carry chains are provided between each of the logic cells of each column. At least one (56) of the logic cells includes one or more Look Up Tables (30A,30B) for implanting logic functions on a set of inputs provided to the one logic cell (56) and an arithmetic logic circuit (24) configured to receive a carry-in signal and to generate a carry-out signal forming part of the first carry chain. The logic cell further includes a first output register (28). An output of the register (28) is provided as an input to one (30A) of the Look Up Tables of the cell through a register feedback connection (60,58). In an embodiment, the set of inputs provided to a first and a second of the Look Up Tables are different, enabling a higher degree of logic efficiency or "packing" by enabling each cell to perform logic functions on two different sets of inputs as opposed to only the same set of inputs. Finally, in another embodiment, the arithmetic logic circuit is capable of generating two SUM output signals.