CLB Logic Cell Architecture for Logic Packing and Fast Carry Chains
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Solution Overview
Problem
Current Complex Logic Block (CLB) based Programmable Logic Devices (PLDs) face limitations in flexibility for performing logic, register, arithmetic functions, and efficiently packing logic functions due to the constraints of existing logic cells.
Innovation Solution
The design incorporates CLBs arranged in rows and columns with enhanced logic cells featuring multiple Look Up Tables, arithmetic logic circuits, and partitioned output registers, including a scan-chain and multiplexers for improved interconnectivity and functionality, allowing for more flexible logic implementation and timing capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional logic cells with single output register are used, then device complexity is reduced, but logic packing efficiency and timing performance deteriorate
Solution Approach 1:
The logic cell is segmented into multiple functional units including first and second output registers, arithmetic logic circuits, and look-up tables. Each segment performs specific functions independently, allowing parallel operation and improved logic packing efficiency while maintaining manageable complexity through functional specialization.
Solution Approach 2:
The logic cell is designed as a multi-functional unit that can perform both arithmetic operations (via arithmetic logic circuits) and logic operations (via look-up tables), with multiple output registers providing versatile output capabilities. This universal design improves packing efficiency by reducing the need for separate dedicated cells for different function types.
2Speed
If conventional interconnect structures are used, then device complexity is minimized, but signal propagation speed deteriorates
Solution Approach 1:
The interconnect structure provides different connection qualities for different signal paths. Carry signals receive dedicated fast carry chains with optimized routing, while other signals use standard interconnects. This local optimization of interconnect quality improves propagation speed for critical paths without unnecessarily increasing overall device complexity.
3Adaptability or versatility
If logic cells with limited register functionality are used, then ease of manufacture is improved, but timing control flexibility deteriorates
Solution Approach 1:
The output registers are designed with dynamic control capabilities including enable inputs and clock selection logic, allowing flexible timing control for different operating modes. The registers can be independently controlled to provide precise timing adjustments while using standard register cell designs that maintain ease of manufacture through proven fabrication processes.
4Speed
If slices in different columns are isolated, then reliability is improved through independence, but arithmetic operation speed deteriorates
Solution Approach 1:
Carry chains are merged across slice boundaries to create unified arithmetic pathways. The carry-out of one slice connects directly to the carry-in of the next slice through optimized carry chain logic, enabling fast multi-slice arithmetic operations while maintaining slice independence for non-arithmetic functions through configurable connection paths.
Data Source
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AI summary
A CLB-based PLD with logic cells (36) having improved logic, register, arithmetic, logic packing and timing functions and capabilities is disclosed. The CLBs of the PLD are arranged in rows and columns of an array and are interconnect by a plurality of interconnect lines. Each of the plurality of CLBs has a first slice of logic cells and a second slice of logic cells arranged in a first column and a second column. First and second carry chains are provided between each of the logic cells of each column. At least one of the logic cells (36) includes one or more Look Up Tables (30A,30B) for implanting logic functions on a set of inputs provided to the one logic cell (36) and an arithmetic logic circuit (24) configured to receive a carry-in signal and to generate a carryout signal forming part of the first carry chain. In one embodiment, the logic cell (36) further includes a first output register (28) and a second output register (38) and the set of outputs generated by the logic cell (36) are partitioned among the first output register (28) and the second output register (38). In another embodiment, an output of one of the registers is provided as an input to one of the Look Up Tables of the cell through a register feedback connection. In yet another embodiment, the set of inputs provided to a first and a second of the Look Up Tables are different, enabling a higher degree of logic efficiency or "packing" by enabling each cell to perform logic functions on two different sets of inputs as opposed to only the same set of inputs. Finally, in another embodiment, the arithmetic logic circuit is capable of generating two SUM output signals.