Clear-Field Reticle Stitching for Overlay-Robust IC Interconnects
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Solution Overview
Problem
Existing photolithography techniques face challenges in combining multiple exposures to form robust interconnections between separate circuit blocks due to overlay misalignments and registration errors, particularly when using negative tone photoresist and clear-field exposures.
Innovation Solution
Employing a clear-field lithographic process with negative tone resist and strategically designed reticles that incorporate extra masking to prevent unintended exposure, allowing for robust interconnect patterns that compensate for overlay errors by flaring feature widths, thereby ensuring consistent line features across exposure fields.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple photolithography exposures are combined to form interconnections spanning separate circuit blocks, then design flexibility and interconnect coverage are improved, but overlay misalignments cause significant interconnect thinning or discontinuities
Solution Approach 1:
The patent applies preliminary action by pre-flaring the line end features before exposure. The reticle patterns include line end features with widths greater than the target line width, creating an intentional overshoot that compensates for expected overlay misalignment. This preliminary geometric compensation ensures that even when fields shift relative to each other, the flared ends maintain continuous interconnect formation without thinning or discontinuities.
2Reliability
If clear-field exposures with negative tone resist are used for stitching, then robust interconnections can be formed, but extra masking is required to prevent unintended exposure
Solution Approach 1:
The patent applies local quality by implementing different masking strategies in different regions of the reticle. Clear-field regions use transparent areas to define features, while dark-field regions use opaque features on transparent backgrounds. The line end features specifically employ clear-field regions with strategic opaque masking to prevent unintended exposure during overlay. This localized differentiation of masking approaches enables robust interconnect formation while managing overall masking complexity through region-specific optimization.
3Ease of manufacture
If standard photolithography fields are used, then manufacturing process is simpler, but IC dies of greater size cannot be formed
Solution Approach 1:
The patent applies segmentation by dividing the large IC die into multiple separately exposed photolithography fields that are subsequently stitched together. Each field can be processed using standard, simpler photolithography techniques, while the overall die size exceeds what a single exposure field could produce. The line end features at field boundaries ensure continuous interconnect formation across these segmented fields, enabling large die fabrication through multiple manageable exposure steps.
4Manufacturing precision
If higher-resolution exposures with smaller fields are used, then feature resolution is improved, but more exposures are required to cover the same area
Solution Approach 1:
The patent applies merging by combining multiple high-resolution exposure fields into a single unified IC die through photolithography stitching. Each individual field delivers high feature resolution with smaller field size, but by strategically overlapping these fields and using line end features for continuous interconnect formation, the final product achieves both high resolution and large overall die area. This merging of multiple high-resolution exposures enables superior feature quality across extended chip dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances manufacturing yield and reliability by reducing critical dimension variations and failures, improves resistance characteristics of signal lines, and enables the use of high-NA systems and materials like negative tone resist for tighter metal interconnects.
Implementation Method 1
negative tone photoresist
Data Source
AI summary
An integrated circuit (IC) device may include features that were patterned using overlapping exposure fields and that span the region of overlap between the exposure fields. The features may be developed from negative tone photoresist exposed using one or more clear-field reticles. A clear-field reticle may include a reflective substrate and absorber features in an opaque mask on the substrate. A single reticle may have complementary portions of an overlapping pattern, e.g., for a line feature, on opposite edges. Complementary portions of an overlapping pattern may be on different reticles.