Cleared Cache Line Tagging to Cut Memory Fetch Traffic

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Solution Overview

Problem

Conventional cache systems consume excessive bandwidth and energy due to unnecessary data fetch requests for cache lines cleared of data, as they lack an efficient mechanism to indicate cleared cache lines, leading to round-trip traffic through the cache hierarchy.

Innovation Solution

Implementing a cleared page tag structure, such as an SRAM cache structure, to track and indicate cleared cache lines, redirecting data fetch requests away from further cache levels and main memory by intercepting and responding to data requests with indications of cleared cache lines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If conventional cache systems process data fetch requests without tracking cleared cache lines, then the cache hierarchy operates with simple structure, but excessive bandwidth and energy are consumed due to unnecessary data fetches to main memory

Engineering Contradiction:
Improveenergy consumptionVSAvoidcache structure complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The system performs preliminary action by tracking and recording which cache lines have been cleared before data fetch requests are processed. The cleared page tag structure pre-stores this information so that when a data fetch request arrives, the system can immediately check whether the requested cache line has been cleared and redirect the request accordingly, avoiding unnecessary trips to main memory and reducing energy consumption

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary structure called the cleared page tag structure that sits between the cache hierarchy and main memory. This intermediary tracks cleared cache lines and intercepts data fetch requests, determining whether requests should be fulfilled from the cleared page tag structure (indicating the data is zeroed) or forwarded to lower cache levels and main memory, thereby reducing unnecessary memory access and energy consumption

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If conventional cache systems process all data fetch requests through the full cache hierarchy, then the cache system maintains simple operation logic, but round-trip traffic increases bandwidth consumption and reduces system performance

Engineering Contradiction:
Improvesystem performanceVSAvoiddata traffic volume
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The system performs preliminary action by pre-tracking which cache lines have been cleared and storing this information in the cleared page tag structure before data fetch requests are processed. This allows the system to immediately recognize and redirect requests for cleared cache lines, preventing them from traversing the full cache hierarchy and reducing overall data traffic volume while improving system performance

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The cleared page tag structure serves as an intermediary that intercepts data fetch requests before they reach the full cache hierarchy. By checking the cleared page tag structure first, the system can identify requests for cleared cache lines and fulfill them directly without routing through multiple cache levels, thereby reducing round-trip traffic and bandwidth consumption while maintaining simple operation logic

Inventive Principle:
Principle #24Intermediary (Mediator)

3Loss of energy

If the system implements tracking of cleared cache lines, then unnecessary data fetches are avoided and energy is conserved, but the cache system requires additional storage structures and increased complexity

Engineering Contradiction:
Improveenergy conservationVSAvoidcache system complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The system performs preliminary action by pre-tracking and recording which cache lines have been cleared in the cleared page tag structure. This advance tracking enables the system to immediately recognize cleared cache lines when data fetch requests arrive, avoiding unnecessary data fetches to main memory and conserving energy without requiring complex real-time analysis during request processing

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary cleared page tag structure that specifically tracks cleared cache lines. This dedicated structure acts as a filter between the cache hierarchy and main memory, allowing the system to identify and handle requests for cleared cache lines differently, thereby conserving energy by avoiding unnecessary memory access while adding only the specific complexity needed for tracking cleared lines rather than overhauling the entire cache system

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12511236B2Storing indications of cleared cache lines
Publication Date: 2025.12.30 ADVANCED MICRO DEVICES INC
  • US12511236B2 patent drawing
  • US12511236B2 patent drawing
  • US12511236B2 patent drawing

AI summary

Storing indications of cleared cache lines is described. In one example, a cache system includes a plurality of cache levels and a cleared page tag structure coupled to a level of the plurality of cache levels that detects a cache line within the plurality of cache levels that is cleared of data. The cleared page tag structure then stores a tag in the cleared page tag structure indicating that the cache line within the plurality of cache levels is cleared of data.