Unidirectional Client Chain for Packet Memory Routing

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Solution Overview

Problem

High-performance switch chips face challenges in routing numerous wide interfaces from peripheral read/write clients to the central packet memory, requiring extensive and costly routing resources and multiple stages of sequential cells to meet clock frequency targets.

Innovation Solution

A packet processing system utilizing a unidirectional client chain where hierarchical clients and a packet memory arbiter are serially communicatively coupled via primary interfaces, allowing all clients to write to or read from the packet memory through this chain, thereby reducing the need for extensive routing and minimizing latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If each client has a dedicated interface to read or write data to/from the packet memory, then the bandwidth requirements of high-performance switch chips can be met, but the number of wires that are needed to be routed from the clients to the PM becomes unfeasibly large

Engineering Contradiction:

ImprovebandwidthVSAvoidnumber of wires

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

Multiple client interfaces are merged into a single shared bus that connects all clients to the packet memory. Instead of providing dedicated point-to-point connections for each client, the patent combines multiple communication channels into one shared medium, reducing the total number of wires while maintaining the ability to serve multiple clients simultaneously through time-multiplexed access.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

An arbiter is introduced as an intermediary component between the clients and the packet memory. The arbiter manages access to the shared bus, allocating time slots to different clients based on their bandwidth requirements. This mediator enables multiple clients to share the single bus interface while maintaining the appearance of dedicated connections, resolving the contradiction between bandwidth needs and wire count.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Ease of manufacture

If read/write clients are physically placed in the periphery of the device while the packet memory is in the middle, then the device layout can be optimized, but the problem of routing many wires between the ports and the PM is exacerbated

Engineering Contradiction:

Improvedevice layoutVSAvoidrouting complexity

Core Design Contradiction:

Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent merges multiple separate wire routes into a single shared bus structure. By consolidating the communication paths from multiple peripheral clients to the central packet memory into one shared medium, the routing complexity is dramatically reduced. This allows the peripheral placement of clients to be maintained for manufacturing ease while avoiding the need to route numerous individual wires across the device.

Inventive Principle:

Principle #5Merging (Combining)

3Speed

If wide interfaces are routed from the periphery of the die to the center of the die, then high data transfer rates can be achieved, but expensive routing resources (top-level metal layers) are required

Engineering Contradiction:

Improvedata transfer rateVSAvoidrouting resources

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

Multiple wide interfaces are merged into a single shared bus that operates through time-multiplexed access. Instead of routing multiple expensive wide interfaces simultaneously across the die, the patent combines them into one shared pathway that serves all clients sequentially. This maintains the high data transfer capability by providing each client with dedicated time slots at full bandwidth while using only a single physical routing resource.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The shared bus operates using periodic time-multiplexed access, where different clients are granted access to the bus in alternating time slots. This periodic allocation of the shared resource to different clients enables each to achieve full bandwidth performance while sharing the same physical routing infrastructure, thereby reducing the total routing resources required compared to simultaneous dedicated connections.

Inventive Principle:

Principle #19Periodic action

4Speed

If several stages of sequential cells are inserted to meet the target clock frequency, then the long interface busses can function, but the latency and complexity of the system increase

Engineering Contradiction:

Improveclock frequencyVSAvoidlatency

Core Design Contradiction:

SpeedVSLoss of time

Solution Approach 1:

The patent merges multiple long interface busses into a single shared bus, thereby eliminating the need for multiple stages of sequential cells that would be required for each separate long connection. By consolidating the communication paths, the system reduces the total number of timing stages needed while still maintaining the necessary clock frequency for reliable operation across the device.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS12298925B2Packet processing system, method and device utilizing a port client chain

Publication Date: 2025.05.13 MARVELL ASIA PTE LTD

AI summary

A packet processing system having each of a plurality of hierarchical clients and a packet memory arbiter serially communicatively coupled together via a plurality of primary interfaces thereby forming a unidirectional client chain. This chain is then able to be utilized by all of the hierarchical clients to write the packet data to or read the packet data from the packet memory.