Client IC PLL Power-On Communication Using Free-Running Clock
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current systems require an accurate clock source at startup for UART communication, which adds design complexity and extends power-on time, especially in battery-powered devices like ATMs, and necessitate upfront clock frequency configuration and storage.
Innovation Solution
A Client IC with a PLL stage that uses an unregulated output clock from a free-running voltage controlled oscillator for initial power-on data communication, allowing configuration data to set up locked clocks without waiting for PLL lock, enabling flexible clock frequencies and reducing power-on time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an accurate clock source is used at startup for UART communication, then communication stability is improved, but device complexity and cost increase
Solution Approach 1:
The patent applies preliminary action by performing baud rate detection and clock configuration during the power-on initialization phase before regular communication begins. The Host IC detects the clock frequency and configures the Client IC's PLL parameters in advance, so that when regular communication starts, the accurate clock synchronization is already established without requiring complex hardware at each communication point.
2Reliability
If an accurate clock source is used at startup, then communication stability is improved, but power-on time is extended
Solution Approach 1:
The patent applies self-service by enabling the Client IC to autonomously acquire accurate clock synchronization through its internal PLL stage. The Host IC sends configuration data including clock frequency information, and the Client IC's PLL automatically locks to the Host IC's clock without requiring external intervention or waiting for complex external clock circuits to stabilize, thus reducing power-on time while maintaining communication stability.
3Measurement precision
If PLL lock is waited for before communication, then clock accuracy is improved, but power-on time is extended
Solution Approach 1:
The patent resolves this contradiction by performing the PLL locking process as a preliminary action during power-on initialization. The Host IC detects the clock frequency and configures the Client IC's PLL parameters before regular communication begins. This way, the PLL lock is achieved in advance, ensuring clock accuracy for subsequent communication without extending the time available for actual data transmission.
4Measurement precision
If upfront clock frequency configuration is required, then clock synchronization is improved, but device complexity and cost increase
Solution Approach 1:
The patent applies self-service by enabling the Client IC to automatically acquire and configure its clock parameters through the PLL stage. The Host IC provides the clock frequency information, and the Client IC's PLL autonomously adjusts its voltage-controlled oscillator to lock onto the Host IC's clock frequency, eliminating the need for manual upfront configuration or complex pre-programming of clock parameters.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables rapid and robust power-on communication without requiring an accurate clock, reducing power consumption and eliminating the need for upfront clock configuration, while being versatile across different applications and communication schemes.
Implementation Method 1
a voltage controlled oscillator for the generation of the clock for the Client IC
Implementation Method 2
a phase detector to detect the phase difference between the clock provided by a Host IC and the clock generated by a voltage controlled oscillator
Implementation Method 3
The detection signal passes a filter and then regulates the clock generated by the voltage controlled oscillator in a loop until both clocks of the Host IC and the clock generated by the PLL stage for the Client IC are locked
Data Source
Figure 1~2
Figure 3~5
AI summary
A system (1) of a Host IC (2) connected via a wired data interface to a Client IC (3) to initiate the communication between the Host IC (2) and the Client IC (3) after power-on, wherein the Client IC (3) comprises a PLL stage (4) with a closed loop of a phase detector (5) a filter (6) and a voltage controlled oscillator (7) for the generation of the clock (C-clk) for the Client IC (3), which PLL stage (4) needs to be locked to the clock (H-clk) of the Host IC (2) for regular data communication via the wired data interface, which Client IC (3) comprises a power-on stage (4) to steer a switch (14) in the connection between the input of the clock (H-clk) of the Host IC (2) for the PLL stage (4) and the voltage controlled oscillator (7) of the PLL stage (4) to open the connection and to use the unregulated output clock of the free-running voltage controlled oscillator (7) in a time period after power-on for a power-on data communication via the wired data interface and to close the switch (14) after that time period for regular data communication.