Clip State Machine for Batch Vertex Culling

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Solution Overview

Problem

Conventional graphics processing pipelines waste memory bandwidth and processing resources by performing operations on all primitives regardless of whether they are clipped or culled later in the pipeline, leading to unnecessary processing of discarded vertices.

Innovation Solution

A method is introduced to generate a clip state for a set of vertices relative to multiple clip planes, determining whether each vertex is inside, outside, or a mix of both, and updating a clip state machine to decide whether to process the vertices, thereby conserving processing bandwidth and reducing computational load on the viewport scale, cull, and clip unit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If operations are performed on all primitives in the graphics processing pipeline, then complete processing coverage is achieved, but memory bandwidth and processing resources are wasted on primitives that will be discarded later

Engineering Contradiction:
Improveprocessing coverageVSAvoidmemory bandwidth and processing resources
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent applies preliminary action by performing clip state generation early in the graphics processing pipeline, before vertex shading and geometry shader operations. The clip state machine determines which primitives will be discarded based on their position relative to clip planes, allowing the system to skip unnecessary processing of primitives that will be culled, thus conserving memory bandwidth and processing resources while maintaining complete processing coverage for visible primitives

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If vertex shading and geometry shader operations are performed on all vertices, then accurate rendering is ensured, but computational load increases for vertices that will be culled

Engineering Contradiction:
Improverendering accuracyVSAvoidcomputational load
Core Design Contradiction:
Manufacturing precisionVSPower

Solution Approach 1:

The patent performs clip state determination as a preliminary action before vertex shading and geometry shader operations. By evaluating vertex positions against clip planes early in the pipeline and storing the clip state, the system can identify and discard primitives that will not contribute to the final image, thereby reducing computational load on subsequent processing stages while ensuring rendering accuracy is maintained for all visible vertices

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent extracts the clip state determination function from the later processing stages and places it in an early stage of the graphics pipeline. This extraction allows the system to separate the culling decision-making process from the rendering operations, enabling early elimination of invisible primitives and reducing the computational burden on vertex shading and geometry shader units

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS8384736B1Generating clip state for a batch of vertices
Publication Date: 2013.02.26 NVIDIA CORP
  • US8384736B1 patent drawing
  • US8384736B1 patent drawing
  • US8384736B1 patent drawing

AI summary

One embodiment of the present invention sets forth a technique for generating a batch clip state stored in clip state machine (CSM) associated with a batch of vertices. Per-vertex clip state is generated for each vertex in the batch of vertices based on the position of each vertex relative to each clip plane. For a given vertex, per-vertex clip state indicates whether the vertex is inside or outside each of the one or more clip planes. The per-vertex clip states of all the vertices in the batch of vertices are coalesced into a batch clip state by determining whether each vertex in the batch of vertices is inside every clip plane, each vertex is outside at least one clip plane or neither. The batch clip state is stored in the CSM associated with the thread group that processes the batch of vertices that can be accessed by further stages of the graphics pipeline.