Clipless Semiconductor Package Using Conductive Film
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Solution Overview
Problem
Semiconductor package platforms using clip bonding face high costs due to expensive clip and bonding equipment, and suffer from inconsistent solder application leading to poor performance, especially as feature sizes decrease.
Innovation Solution
A clipless and wireless semiconductor die package is developed, using a conductive film to electrically couple leadframe structures to semiconductor dies, reducing material and manufacturing costs while maintaining thermal and electrical performance advantages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clip bonding is used to electrically connect semiconductor die to leadframe, then thermal and electrical properties are improved, but manufacturing cost and material cost increase significantly
Solution Approach 1:
The patent removes the clip component entirely from the packaging structure, extracting only the essential function of electrical connection. Instead of using a separate clip element that requires specialized bonding equipment, the invention integrates the electrical connection function directly into the molding compound through embedded conductive pathways, thereby eliminating the need for clip bonding processes and associated high equipment costs.
Solution Approach 2:
The molding compound serves multiple functions: it provides mechanical support, thermal management, electrical insulation, and electrical connection pathways. By embedding conductive materials within the molding compound, the same material that provides structural support and thermal management also establishes electrical connections, eliminating the need for separate clip components and bonding processes.
2Reliability
If clip bonding is used to electrically connect semiconductor die to leadframe, then electrical connection is achieved, but solder application consistency deteriorates
Solution Approach 1:
The patent introduces an intermediary conductive layer within the molding compound that facilitates electrical connection between the semiconductor die and leadframe. This embedded conductive pathway acts as a mediator that ensures consistent electrical connectivity without requiring precise solder application, as the conductive material is uniformly distributed within the molding compound during the molding process rather than requiring subsequent soldering steps.
3Length of moving object
If feature sizes of MLP components are reduced, then device miniaturization is achieved, but metal-to-metal clearance and dimensional tolerance become insufficient
Solution Approach 1:
The patent transitions from planar metal-to-metal connections to three-dimensional embedded conductive pathways within the molding compound. By utilizing the vertical dimension and distributing conductive material throughout the volume of the molding compound, the invention achieves electrical connections that are not constrained by surface clearance limitations, allowing for reduced feature sizes while maintaining adequate electrical isolation and connection reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly decreases material and manufacturing costs, ensures consistent electrical connections, and maintains low on-resistance and high current-carrying capabilities, addressing the limitations of clip-bonded packages.
Implementation Method 1
forming a layer of conductive material on the lead surface and the first surface of the semiconductor die to electrically couple the at least one lead structure to the semiconductor die
Data Source
AI summary
A method for making a semiconductor die package is disclosed. In some embodiments, the method includes using a leadframe structure including at least one lead structure having a lead surface. A semiconductor die having a first surface and a second surface is attached to the leadframe structure. The first surface of the semiconductor die is substantially planar to the lead surface and the second surface of the semiconductor die is coupled to the leadframe structure. A layer of conductive material is formed on the lead surface and the first surface of the semiconductor die to electrically couple the at least one lead structure to the semiconductor die.