Clock Duty Cycle Adjuster Setting with Monitor Offset Boundaries
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor memories face issues with duty cycle distortion in clock timing, leading to erroneous operations, as existing duty cycle adjuster circuits require accurate settings to effectively improve duty cycle, but may not suffice unless set accurately.
Innovation Solution
A duty cycle monitor (DCM) and duty cycle adjuster (DCA) feature is introduced, allowing for precise monitoring and adjustment of internal clock duty cycles through a mode register, enabling accurate timing adjustments to compensate for duty cycle errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If duty cycle adjuster circuits are used to adjust duty cycle of internal clocks, then duty cycle can be improved, but the adjustment is not sufficient unless the adjuster circuits are set accurately
Solution Approach 1:
The patent implements a feedback mechanism where the memory device monitors its own clock duty cycle performance and automatically adjusts the duty cycle adjuster circuit settings based on measured deviations. The memory device sends feedback information to the memory controller indicating the current duty cycle status, and the controller responds by adjusting settings to maintain optimal duty cycle without requiring manual calibration
Solution Approach 2:
The memory device performs self-diagnosis and self-adjustment of clock duty cycle parameters. The device autonomously measures its own clock signal characteristics, identifies duty cycle distortion, and modifies its internal clock timing without external intervention, enabling the system to maintain accuracy without complex manual setup procedures
2Measurement precision
If accurate duty cycle adjustment is implemented, then clock timing precision is improved, but the system complexity increases due to monitoring and adjustment mechanisms
Solution Approach 1:
The duty cycle monitor and adjuster circuit are integrated into the existing memory device architecture, serving multiple functions including clock generation, timing control, and duty cycle adjustment. This multi-functionality approach avoids adding separate dedicated monitoring and adjustment systems, thereby maintaining clock timing precision while minimizing increases in overall device complexity
Solution Approach 2:
The patent combines the duty cycle monitoring, measurement, and adjustment functions into a unified integrated circuit block within the memory device. By merging these functions rather than implementing them as separate systems, the patent achieves precise clock timing control while reducing the complexity that would arise from multiple independent components
Data Source
AI summary
Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.