Clock Duty Cycle Adjuster Calibration Using Monitor Offset Boundaries
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Solution Overview
Problem
Semiconductor memories face issues with duty cycle distortion in clock timing, leading to erroneous operations due to deviations from the ideal 50% duty cycle, which existing duty cycle adjuster circuits may not adequately address without accurate settings.
Innovation Solution
The implementation of a duty cycle monitor (DCM) and duty cycle adjuster (DCA) feature within a mode register allows for precise adjustment of internal clock duty cycles by monitoring duty cycle distortion and adjusting the DCA settings based on DCM results, ensuring accurate timing and reducing errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If duty cycle adjuster circuits are used to adjust internal clock duty cycle, then duty cycle distortion is reduced, but the adjuster settings may not be accurate enough to achieve sufficient improvement
Solution Approach 1:
The patent implements a feedback mechanism where the duty cycle monitor continuously measures the actual duty cycle of internal clocks and provides this information back to the controller. The controller then adjusts the duty cycle adjuster settings based on this feedback to achieve the target 50% duty cycle, resolving the contradiction between adjuster capability and measurement precision by creating a closed-loop control system.
Solution Approach 2:
The patent replaces manual or fixed duty cycle adjuster settings with an automated electronic control system. The controller electronically adjusts the duty cycle adjuster settings based on real-time monitoring data, substituting mechanical or static adjustment methods with dynamic electronic control to achieve higher precision.
2Reliability
If duty cycle adjuster settings are made more aggressive to compensate for distortion, then duty cycle improvement increases, but timing errors may be introduced
Solution Approach 1:
The feedback mechanism allows the controller to monitor the actual duty cycle and make fine-grained adjustments rather than applying aggressive fixed corrections. This prevents timing errors by continuously verifying that adjustments are moving the duty cycle toward the target without introducing new timing issues.
Solution Approach 2:
The system applies partial adjustments iteratively rather than excessive single-step corrections. The duty cycle adjuster makes incremental changes based on monitoring feedback, avoiding the timing errors that result from overly aggressive adjustments while still achieving the desired duty cycle correction.
3Reliability
If multiple duty cycle adjusters are used for different clock domains, then overall duty cycle control improves, but device complexity increases
Solution Approach 1:
The controller serves multiple functions: it operates the memory device, monitors duty cycle through the monitor circuit, and adjusts duty cycle settings. This universal controller manages multiple clock domains without requiring separate control circuits for each domain, improving comprehensive duty cycle control while limiting the increase in device complexity.
Solution Approach 2:
The patent merges the duty cycle monitoring and adjustment functions into a unified control system. The controller integrates the monitoring of multiple clock domains and coordinates adjustments across different duty cycle adjusters, combining what could be separate complex systems into a coordinated unified approach.
Data Source
AI summary
Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.