Clock Adjusting Device Using Dual Comparators for Noise Rejection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional USB devices face issues with noise interference affecting clock signal corrections, leading to incorrect adjustments and increased manufacturing costs due to the use of large inductor-capacitor oscillators.
Innovation Solution
A clock adjusting device employing a count comparator and a threshold comparator to perform double comparisons, determining and eliminating noise-affected correction values, thereby ensuring accurate clock signal adjustments without altering the oscillator's frequency when noise interference is detected.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional inductor-capacitor oscillator is used to generate the operation clock signal, then the clock signal can be generated, but the chip area occupied is large and manufacturing cost increases
Solution Approach 1:
The patent uses a ring oscillator to generate the operation clock signal instead of a conventional inductor-capacitor oscillator. The ring oscillator implements the same clock generation function but with significantly reduced chip area, as it uses only transistors and inverters rather than large inductor and capacitor components.
2Device complexity
If a simple comparator is used to compare clock signals, then the device complexity is low, but noise interference cannot be eliminated from correction values
Solution Approach 1:
The patent divides the clock adjustment function into two independent comparison stages: a first comparator that performs initial comparison and a second comparator that performs threshold-based validation. This segmentation allows the system to eliminate noise-affected correction values while maintaining reasonable device complexity, as each comparator remains structurally simple but their combined operation achieves noise rejection.
3Reliability
If the operation clock signal is continuously adjusted based on clock comparison, then clock synchronization is improved, but noise-affected corrections cause incorrect adjustments
Solution Approach 1:
The patent implements a feedback mechanism where the second comparator validates correction values before they are applied to adjust the ring oscillator's frequency. The threshold comparison provides a feedback check that prevents noise-affected corrections from being applied, ensuring that only valid corrections within the acceptable range modify the clock frequency, thus maintaining both synchronization and accuracy.
Data Source
AI summary
A clock adjusting device includes an oscillator, a first counter, a second counter, a count comparator and a threshold comparator. The oscillator transmits an operation clock signal. The first counter counts a reference clock signal, to obtain a reference clock count value. The second counter counts the operation clock signal to obtain an operation clock count value. The count comparator compares the reference clock count value with the operation clock count value, to obtain a candidate correction value. The oscillator adjusts the operation clock signal according to an output correction value. The threshold comparator compares the candidate correction value and an updated threshold. When the candidate correction value is lower than the updated threshold, the candidate correction value is used as the output correction value, and when the candidate correction value exceeds the updated threshold, a current correction value is used as the output connection value.