Clock Alignment Module for Reset Isolation and Phase Recovery
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Solution Overview
Problem
Integrated circuit (IC) systems face challenges in regaining phase alignment of peripherals when one or more peripherals are reset, leading to misalignment and potential performance issues in synchronous systems.
Innovation Solution
The introduction of a clock alignment module that receives a clock bypass signal to switch subcircuits between a reference clock and a second clock signal, generating an alignment signal based on the reference clock frequency, and unblocks the clock signal when alignment is achieved, ensuring synchronized operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a clock bypass signal is used to switch subcircuits between reference clock and second clock signal during reset, then reset isolation is achieved, but clock phase alignment is lost
Solution Approach 1:
The system performs preliminary actions by blocking the clock signal before the reset transition occurs and preparing the alignment signal generation in advance. The clock alignment module proactively monitors the clock bypass signal and prepares to restore alignment once the reset condition is detected, ensuring that phase alignment is reestablished immediately after reset without waiting for drift to accumulate.
Solution Approach 2:
The clock alignment module acts as an intermediary between the clock bypass mechanism and the subcircuits. It receives the clock bypass signal, generates the alignment signal based on the reference clock frequency, and uses this alignment signal to control the clock enable signal that gates the clock to subcircuits. This intermediary ensures that even when the clock bypass switches between reference clock and second clock signal, the subcircuits receive properly aligned clock edges.
2Manufacturing precision
If clock signal is blocked during reset to maintain alignment, then phase synchronization is maintained, but system productivity decreases
Solution Approach 1:
The system uses periodic action by generating alignment signals at regular intervals based on the reference clock frequency. The clock alignment module periodically restores the clock signal to subcircuits synchronized with the reference clock, allowing brief controlled blocking during transitions while maintaining overall continuous operation. This periodic restoration ensures phase synchronization is maintained without requiring continuous clock blocking.
Solution Approach 2:
The system dynamically adjusts the clock signal delivery based on the reset state. The clock alignment module continuously monitors the clock bypass signal and dynamically controls the clock enable signal to block or unblock the clock to subcircuits as needed. This dynamic control allows the system to maintain phase synchronization only when necessary (during reset transitions) while allowing normal operation to proceed without interruption otherwise.
3Manufacturing precision
If alignment signal frequency is predetermined based on clock frequencies, then clock divider synchronization is achieved, but adaptability to different clock configurations is reduced
Solution Approach 1:
The system changes parameters by allowing the alignment signal frequency to be predetermined based on specific clock frequency relationships (such as when the second clock is a divided version of the reference clock). The clock alignment module uses these predetermined frequency relationships to generate alignment signals that synchronize clock dividers. While this provides precise synchronization for common configurations, the system can be adapted to different clock configurations by adjusting the predetermined frequency ratios or adding configuration registers to define the relationship between reference clock and second clock frequencies.
Data Source
AI summary
An electronic device comprising one or more subcircuits configured to receive a clock signal, the clock signal configured to switch from a reference clock signal to a second clock signal based on a clock bypass signal, a timer configured to receive the reference clock signal and output an alignment signal based on the reference clock signal, wherein a frequency of the alignment signal is determined based on clock frequencies of the one or more subcircuits; a clock alignment module coupled to the timer and the one or more subcircuits and configured to receive the clock bypass signal, determine that the clock bypass signal has changed to switch the one or more subcircuits to the reference clock signal from the second clock signal, block the clock signal from being received by the one or more subcircuits, receive the alignment signal, and unblock the clock signal based on the alignment signal.