Output Divider Clock Alignment Using Time-Code Error Correction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing clock generators using phase-locked loops struggle to maintain synchronous frequencies and phases for multiple output clock signals, especially when fractional divider values are involved, due to differing bandwidth and loop characteristics in each phase-locked loop.
Innovation Solution
A clock generator design that includes a loop filter to generate a filtered phase difference signal, using this signal to control output dividers and an error correction circuit to align output clock signals, with output dividers configured in a pseudo-cascaded arrangement to correct phase misalignments and ensure synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If distinct phase-locked loops are used for each independently synthesized clock signal, then frequency synthesis flexibility is improved, but phase synchronization between output clock signals deteriorates
Solution Approach 1:
The system segments the clock generation function by using distinct phase-locked loops for different output clock signals, allowing each loop to be independently configured for frequency synthesis flexibility while maintaining phase synchronization through the shared reference clock and coordinated divider control
Solution Approach 2:
The system implements feedback mechanisms where the phase detector continuously monitors phase differences between reference and feedback clock signals, and the loop filter adjusts the controlled oscillator accordingly to maintain phase synchronization across multiple output clocks while allowing frequency flexibility
2Adaptability or versatility
If different bandwidth and loop characteristics are used in phase-locked loops, then individual clock signal optimization is improved, but phase relationship stability between multiple clock signals deteriorates
Solution Approach 1:
Each phase-locked loop is configured with locally optimized bandwidth and loop characteristics tailored to its specific output clock signal requirements, while the shared reference clock and coordinated control mechanisms ensure that phase relationship stability is maintained across all outputs despite local variations
3Measurement precision
If fractional divider values are used, then frequency precision is improved, but phase alignment between multiple output clocks deteriorates
Solution Approach 1:
The system performs preliminary phase alignment by using a shared reference clock and coordinating the operation of multiple phase-locked loops before output, ensuring that even when fractional divider values are used for precise frequency control, the phase alignment between multiple output clocks is maintained through pre-synchronization mechanisms
Data Source
AI summary
A method includes generating a filtered phase difference signal based on a reference clock signal and a feedback clock signal. The method includes generating a first output clock signal based on a first divider control signal and an input clock signal. The feedback clock signal is based on the first output clock signal. The method includes generating a first time code based on a counter signal and a first update of the first output clock signal in response to an update of the filtered phase difference signal to a first value from a second value. The second output clock signal is based on a second divider control signal, the input clock signal, and an error correction signal generated based on the first value, the second value, the first time code, and the second time code. The first and second divider control signals are based on the filtered phase difference signal.