Source Synchronous Clock Alignment via Training Sequence
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Solution Overview
Problem
Conventional PCIe compliance setups for electronic design IP face inefficiencies due to large board delays and variable skew between testchips and FPGA devices, requiring manpower-intensive manual adjustments for clock alignment, which are not consistent across different testchips due to PVT variations.
Innovation Solution
Implement phase locking for clocks between test subjects and controller devices using a training sequence, with alignment logic on both devices, allowing for transmit and receive phase offset corrections to be performed together or separately, utilizing PRBS generators and checkers to achieve clock alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual MMCM offset adjustment is used for clock alignment, then clock synchronization can be achieved, but the process becomes manpower-intensive and time-consuming
Solution Approach 1:
The system performs self-alignment through automated training sequences where the DUT and controller autonomously adjust their clocks to achieve synchronization, eliminating the need for manual MMCM offset adjustments by engineers
Solution Approach 2:
The alignment logic uses feedback from training sequence results to automatically adjust clock offsets, with the system monitoring synchronization status and iteratively refining the alignment until optimal timing is achieved
2Reliability
If manual clock alignment is performed for each testchip, then acceptable results can be obtained, but the process must be repeated for every testchip due to PVT variations
Solution Approach 1:
The system performs preliminary training sequences during chip initialization to pre-establish optimal clock offsets for each specific testchip before production testing begins, accounting for that chip's unique PVT characteristics
Solution Approach 2:
The system dynamically adjusts clock offset parameters based on training sequence measurements for each individual testchip, adapting to PVT variations without requiring manual re-calibration for each device
3Speed
If single cycle timing closure is attempted between TC and FPGA, then fast testing is possible, but large board delays and variable skew make it impossible
Solution Approach 1:
The system transitions from static single-cycle timing to dynamic multi-cycle training sequences that can adapt to varying board delays and skew, allowing the system to find optimal timing through iterative adjustment rather than requiring precise initial timing closure
Data Source
AI summary
Disclosed is an improved approach to implement clock alignments between a test subject and its corresponding controller device. Phase locking is performed for the clocks between the test subject and controller device via a training sequence to obtain the appropriate alignment(s). Alignment logic is included on both the testchip and the controller device to implement alignment.