Clock Allocation for Programmable Devices
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Solution Overview
Problem
Current electronic design automation (EDA) tools face challenges in efficiently allocating clock resources on programmable devices, such as FPGAs and ASICs, which can lead to suboptimal performance and resource utilization due to restrictive clock allocation constraints that hinder retiming operations.
Innovation Solution
A method and apparatus for performing clock allocation during compilation that allows for flexible definition of clock networks based on physical placement of sequential elements, enabling minimization of clock resources and reducing clock insertion delay, while facilitating high-performance system design with minimal constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional clock allocation is performed with predefined constraints, then clock resource allocation is simplified, but retiming operations are hindered and system performance deteriorates
Solution Approach 1:
The patent performs clock allocation after placement and retiming operations are completed, rather than imposing constraints earlier in the design flow. This allows the clock allocation to be based on the actual final positions of sequential elements and the actual retiming results, eliminating the need for restrictive preliminary constraints while maintaining effectiveness of retiming operations.
Solution Approach 2:
The patent implements a dynamic clock allocation approach where clock network definitions are generated based on the actual placement results and retiming operations. The clock allocation adapts to the final configuration of the design rather than being fixed by predefined constraints, allowing flexibility in clock resource usage while supporting effective retiming.
2Productivity
If clock networks are defined with fixed granularity (quadrant, half-chip, entire chip), then clock allocation is simplified, but resource utilization efficiency deteriorates
Solution Approach 1:
The patent defines clock networks with precise boundaries that exactly enclose the sequential elements belonging to each clock domain, rather than using fixed granular regions. This localizes the clock network definition to the exact area needed, eliminating waste of clock resources in unused regions while maintaining simple and clear clock network definitions based on the actual distribution of sequential elements.
3Productivity
If clock allocation is performed before placement optimization, then clock resource allocation is determined early, but placement flexibility and system performance deteriorate
Solution Approach 1:
The patent performs clock allocation after placement optimization is completed, allowing the placement to be fully optimized first. The clock allocation then uses the optimized placement results to define accurate clock networks, ensuring that placement flexibility is maintained while clock allocation is performed at the appropriate time in the design flow.
Data Source
AI summary
A method for designing a system on a target device includes placing the system on the target device. A netlist retiming is performed on the placed system. A clock allocation and a clock region optimization are performed utilizing information from the placing and the netlist retiming.