Clock-Based Analog Reference Voltage for Distributed LDO Control
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Solution Overview
Problem
Modern computer processor cores face limitations in achieving high operating frequencies due to minimum dropout in low-dropout voltage regulator (LDO) designs, particularly in high-performance power states, where the inherent resistance of the power delivery network (PDN) acts as a bottleneck.
Innovation Solution
The implementation of finely-distributed power gates, a distributed linear regulator with low area overhead, and a diode-based retention mode addresses the IR dropout issue. This includes a special-purpose comparator and a metastability tolerant Delay Locking Loop (DLL)-based digital-to-analog converter (DAC) to generate an analog reference voltage, enabling effective current sharing and minimizing IR gradients.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If distributed LDOs with PFET headers are arranged in rows with wide separation to reduce RPDN, then voltage regulation performance is improved, but current carrying capacity is limited due to max current limits of vias and bumps
Solution Approach 1:
The patent divides the power delivery network into multiple distributed LDO clusters arranged in a mesh-like pattern, with each cluster containing multiple PFET headers. This segmentation allows current to be distributed across multiple pathways rather than funneled through limited top and bottom rows, increasing overall current carrying capacity while maintaining voltage regulation performance through local regulation at each cluster.
Solution Approach 2:
The patent transitions from a conventional two-row topology (top and bottom) to a two-dimensional mesh-like network arrangement. This dimensional change enables current to flow through multiple horizontal and vertical pathways across the die, effectively increasing current carrying capacity without increasing separation distance between PFET headers in any single direction.
2Power
If PFET header separation is reduced in a mesh-like network to increase current capacity, then current carrying capacity is improved, but RPDN becomes a bottleneck increasing dropout
Solution Approach 1:
The patent implements local voltage regulation at each distributed LDO cluster, where each cluster independently regulates its local power domain. This local quality approach ensures that even with reduced PFET header separation in a mesh network, each cluster maintains optimal voltage regulation performance by regulating locally rather than relying on distant regulation points, preventing RPDN from becoming a bottleneck.
3Reliability
If conventional LDO mechanisms are used in low-power states, then voltage regulation is maintained, but regulator controller power consumption overhead negates leakage power savings
Solution Approach 1:
The patent extracts the regulator controller from the low-power path in C1 retention state by implementing clock gating and removing the regulator controller overhead. The system transitions to a retention mode where state is maintained through retention circuits without active regulation, eliminating the power consumption overhead of the regulator controller while preserving leakage power savings in low-power states.
4Reliability
If top and bottom rows of PFETs with thick package layers are used to minimize RPDN, then voltage regulation performance is improved, but scalability is limited as core size increases with increasing current demands
Solution Approach 1:
The patent segments the power delivery network into multiple distributed LDO clusters arranged in a scalable mesh-like pattern. Each cluster is an independent functional unit that can be replicated and distributed across the die as core size increases. This modular segmentation allows the system to scale to larger core sizes and higher current demands by simply adding more clusters to the mesh network rather than relying on fixed top and bottom rows.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed power delivery mechanisms achieve the lowest IR drop in high-performance modes and minimize power consumption overhead in low-power states, while maintaining a lower circuit area compared to conventional solutions.
Implementation Method 1
a metastability tolerant Delay Locking Loop (DLL)-based digital-to-analog converter (DAC) to generate an analog reference voltage
Implementation Method 2
a diode-based retention mode for the lowest-power (e.g., C1) state(s)
Implementation Method 3
the inherent resistance of the PDN (RPDN) becomes a bottleneck
Implementation Method 4
Device (e.g., PFET) headers between the global and local power domains
Data Source
AI summary
Reference voltage generators including a header circuit configured to pass current from a power supply to a time-to-digital converter, an amount of the current to pass determined by a thermometer code, and logic to update the thermometer code based on a comparison between an output of the time-to-digital converter and a digital code representing a reference voltage level.