Clock Signal Anomaly Detection With Dynamic Phase Calibration
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Solution Overview
Problem
Digital systems face challenges in detecting and responding to clock anomalies, such as clock stops and glitches, which can lead to unexpected behavior and security vulnerabilities due to the lack of effective anomaly detection mechanisms.
Innovation Solution
A clock anomaly detection system that utilizes clock stopped low and high detectors to identify anomalies by monitoring the duration of clock signal phases and asserting a reset signal when anomalies are detected, with dynamic calibration to minimize latency and account for PVT variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If clock anomaly detection is implemented using fixed timing thresholds, then the detection mechanism is simple, but detection accuracy deteriorates under PVT variations
Solution Approach 1:
The patent implements dynamic calibration of timing thresholds based on actual clock signal measurements. The system adjusts the expected high and low phase durations adaptively to account for PVT variations, transforming the fixed threshold approach into a dynamic one that maintains detection accuracy across different operating conditions.
Solution Approach 2:
The system changes the timing threshold parameters dynamically by measuring actual clock phase durations and adjusting the expected high and low phase durations accordingly. This parameter adaptation allows the detection mechanism to maintain precision despite process, voltage, and temperature variations.
2Measurement precision
If dynamic calibration is implemented to account for PVT variations, then anomaly detection accuracy is improved, but device complexity increases
Solution Approach 1:
The system performs self-calibration by automatically measuring its own clock signal characteristics and adjusting its timing thresholds without external intervention. The calibration unit measures actual high and low phase durations and uses these measurements to update the expected durations, enabling the system to adapt to PVT variations autonomously.
Solution Approach 2:
The patent implements a feedback mechanism where the measured clock phase durations are fed back to adjust the expected timing thresholds. The system continuously monitors actual performance and uses this information to refine its detection criteria, creating a closed-loop system that maintains accuracy under varying conditions.
3Measurement precision
If timing thresholds are set to be highly sensitive to detect anomalies, then detection precision is improved, but false positive rate increases
Solution Approach 1:
The system performs preliminary calibration by measuring actual clock signal characteristics before establishing detection thresholds. By pre-adjusting the expected high and low phase durations based on real measurements, the system sets accurate baseline values that prevent both false positives and missed detections, rather than using fixed or overly sensitive thresholds.
Data Source
AI summary
Methods and apparatus are described for detecting anomalies in a clock signal. Example methods include sensing a clock signal that exhibits alternating phases during normal operation; responsive to sensing the start of a first phase, generating a pulse; and if the pulse terminates before sensing the end of the first phase, asserting a clock stopped detection signal. Example clock anomaly detection apparatus includes a clock signal input for coupling to a clock signal that, during normal operation, oscillates between first and second clock states. An anomaly detection output is asserted if the clock signal remains in the first clock state longer than a first phase expected duration or remains in the second clock state longer than a second phase expected duration.