Clock Arbitration Circuit for Secure Synchronization Detection
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Solution Overview
Problem
Existing time arbitration circuits in computer networks face challenges in ensuring the accuracy and security of clock signals, particularly due to environmental factors like climatic conditions and vibrations, which can lead to synchronization issues and potential malicious acts, impacting critical applications such as air traffic control and banking transactions.
Innovation Solution
A time arbitration circuit with a comparator and a clock signal generator, utilizing high-stability quartz oscillators or atomic micro-oscillators, compares input signals to detect synchronization and potential faults, and a control circuit authorizes or blocks the output clock signal based on synchronization state, ensuring secure and reliable time distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a time base is used to define time within an electronic device, then time tracking is enabled, but accuracy deteriorates due to drift caused by environmental factors such as weather conditions and vibrations
Solution Approach 1:
The patent introduces a reference time source as an intermediary element that mediates between the imperfect internal time base and the required accurate time tracking. The reference time source serves as a stable mediator that corrects drift in the internal time base, enabling accurate time tracking without being affected by environmental factors directly
Solution Approach 2:
The patent implements a feedback mechanism where the time arbitration circuit continuously monitors the internal time base against the reference time source and adjusts the time tracking accordingly. This feedback loop compensates for drift caused by environmental factors, maintaining measurement precision while allowing the use of simpler internal time bases
2Reliability
If multiple synchronization sources are used to ensure secure clock signals, then security and reliability improve, but device complexity increases due to the need for arbitration circuits and signal comparison
Solution Approach 1:
The patent segments the synchronization function into distinct modules: multiple independent synchronization sources, a time arbitration circuit for comparing signals, and a control circuit for decision-making. This segmentation allows each component to perform its specific function efficiently, reducing overall system complexity while maintaining security through diversified time sources
Solution Approach 2:
The patent applies partial action by implementing arbitration only when synchronization status needs verification, rather than continuously processing all signals. The control circuit makes decisions based on arbitration results without requiring complex continuous intervention, reducing device complexity while maintaining clock signal security
3Difficulty of detecting and measuring
If signal comparison is performed to detect synchronization issues, then detection capability improves, but loss of time occurs due to the comparison and arbitration process
Solution Approach 1:
The patent implements periodic signal comparison and arbitration rather than continuous processing. The time arbitration circuit performs synchronization status detection at regular intervals, enabling detection of synchronization issues while minimizing the time lost to arbitration operations. This periodic action balances detection capability with time efficiency
Data Source
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AI summary
The time arbitration circuit (1) includes: a comparator (2) including at least first and second inputs and configured to deliver at least one first piece of information (D) relating to the synchronisation state of the signals (C1, C2) present on the first and second inputs; a clock-signal generator (G) that is connected to an output terminal (O) of the time arbitration circuit (1) and that delivers an output clock signal (CO); a control circuit (3) that is configured to permit or block the delivery of the output clock signal (CO) to the output terminal depending on the first piece of information (D) of the comparator (2) and possibly to deliver a piece of information relating to the synchronisation state depending on the first piece of information (D); the first and second inputs of the comparator are connected to first and second input terminals (I1, I2) of the time arbitration circuit (1), which terminals are intended to be connected to first and second sources (S1, S2) delivering the first and second clock signals (C1, C2).