Dynamic Clock Auto-Phasing for Supply Noise Jitter Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods, such as static delay elements, are ineffective in minimizing clock jitter in integrated circuit (IC) devices due to process variations and unpredictable operating conditions, particularly in user-configurable devices like programmable logic devices (PLDs), where the temporal relationship between switching events is unknown.
Innovation Solution
A dynamic control circuit that monitors supply voltage fluctuations and adjusts the triggering of switching events in IC devices to occur during relatively quiet time intervals, using detection circuits and adjustable delay or phase-locked loops to phase-shift clock signals and reduce jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a static delay element is used to minimize clock jitter, then the timing of switching events can be fixed to avoid supply voltage fluctuations, but the system cannot compensate for process variations and operating condition changes
Solution Approach 1:
The patent applies dynamics by transitioning from a static delay element to a dynamic control system that continuously monitors supply voltage fluctuations and adjusts clock signal phase in real-time. The control circuit modifies the phase of clock signals based on detected voltage variations, enabling the system to adapt to changing operating conditions and process variations while maintaining clock jitter minimization.
2Reliability
If a static delay element is used to maintain predetermined phase delay, then clock jitter may be reduced in known configurations, but the approach produces unpredictable results in user-configurable devices with unknown temporal relationships
Solution Approach 1:
The patent implements feedback by using a control circuit that continuously monitors supply voltage fluctuations and uses this information to dynamically adjust the phase of clock signals. This closed-loop feedback mechanism eliminates the need for predetermined knowledge of temporal relationships between circuit blocks, making the system equally effective for both fixed and user-configurable devices while maintaining clock jitter reduction.
3Ease of manufacture
If switching events are triggered during noisy time intervals, then circuit operation is simplified, but supply voltage fluctuations cause timing errors and device malfunction
Solution Approach 1:
The patent applies preliminary action by proactively adjusting the phase of clock signals before switching events occur during noisy time intervals. The control circuit detects supply voltage fluctuations and advances or delays clock signal phases in advance, ensuring that switching events are triggered during relatively quiet time intervals when supply voltage is stable, thereby preventing timing errors while maintaining circuit operation simplicity.
Data Source
AI summary
The relative timing of triggering switching events in a circuit block of an IC device is dynamically adjusted in response to fluctuations in device's supply voltage to minimize clock jitter caused by supply voltage noise. A control circuit monitors supply voltage fluctuations, and in response thereto dynamically phase-shifts a clock signal that triggers the switching events so that the switching events occur during relatively quiet time intervals in which fluctuations in the supply voltage are minimal.