Reset Signal Generation Circuit for Clock-Aware Initialization
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Solution Overview
Problem
Existing semiconductor devices face issues with data loss and improper initialization due to the generation of asynchronous reset signals during power supply voltage fluctuations, which can lead to abnormal operation and failure in initializing synchronous circuits.
Innovation Solution
A reset signal generation circuit that detects the operation state of synchronous circuits and generates reset signals that are either synchronous or asynchronous to the clock signal based on the operation state, ensuring proper initialization and data preservation by using an operation detection circuit, signal control circuit, oscillation stabilization control, and determination circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a reset signal is generated asynchronously to the system clock signal when the system clock signal is not generated, then the semiconductor device can be initialized during power supply voltage fluctuations, but data stored in synchronous circuits may be lost during normal operation
Solution Approach 1:
The reset signal generation circuit dynamically switches between asynchronous and synchronous reset signal generation modes based on the operation state of the oscillation circuit. When the oscillation circuit is abnormal (no clock signal), asynchronous reset is enabled for reliable initialization. When the oscillation circuit is normal (clock signal present), synchronous reset is used to preserve data in synchronous circuits.
Solution Approach 2:
The circuit changes the timing parameter of the reset signal relative to the clock signal based on operating conditions. The reset signal can be either asynchronous (when clock is absent) or synchronous (when clock is present), adapting the phase relationship between reset and clock signals according to the operational state of the system.
2Loss of information
If a reset signal is generated synchronously to the system clock signal when the system clock signal is generated, then data stored in synchronous circuits is preserved, but the semiconductor device may fail to initialize when the internal circuit is operating abnormally
Solution Approach 1:
The reset signal generation circuit dynamically switches between asynchronous and synchronous reset signal generation modes based on the operation state of the oscillation circuit. When the oscillation circuit is abnormal (no clock signal), asynchronous reset is enabled for reliable initialization. When the oscillation circuit is normal (clock signal present), synchronous reset is used to preserve data in synchronous circuits.
Solution Approach 2:
The operation detection circuit monitors the oscillation circuit's operation state and provides feedback to the reset signal generation circuit. This feedback mechanism enables the system to detect when the oscillation circuit is abnormal and automatically switch to asynchronous reset mode to ensure proper initialization, while normally operating in synchronous mode to preserve data.
3Reliability
If the reset signal generation circuit monitors power supply voltage continuously, then the semiconductor device can respond to voltage fluctuations, but the circuit complexity increases
Solution Approach 1:
The operation detection circuit serves multiple functions: it detects both the presence of the system clock signal and the operation state of the oscillation circuit, and generates control signals for the reset signal generation circuit. This multi-functionality reduces the need for separate dedicated monitoring circuits, thereby limiting the increase in circuit complexity while maintaining reliable voltage and operation monitoring.
Data Source
AI summary
A reset signal generation circuit for generating a reset signal synchronously or asynchronously to a clock signal in accordance with an operation state. An operation detection circuit detects operation of a CPU and generates an operation detection signal. A signal control circuit generates a first reset signal synchronously or asynchronously to an internal clock signal based on the operation detection signal and a system reset signal. The first reset signal is provided to synchronous circuits including the CPU.