Clock-Aware Simulation Vector Processor for Parallel 4-State Verification
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Solution Overview
Problem
The computational intensity of logic simulation processes increases with the size of circuit designs, particularly when using a 4-state model, leading to inefficiencies in verifying functional correctness and design intent.
Innovation Solution
A simulation vector processor system employing a parallel hardware implementation and 4-state model to verify circuit designs, utilizing a flow processor and evaluation system with instruction memory, interconnect circuitry, and operation circuitry to efficiently simulate and detect errors in circuit operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional logic simulation methods are used to verify circuit designs, then functional correctness can be verified, but verification time increases significantly with circuit size
Solution Approach 1:
The patent divides the circuit design into multiple testable modules or units, each can be verified independently. The evaluation system processes different portions of the circuit design in parallel, segmenting the verification task to reduce overall verification time while maintaining comprehensive functional correctness checking.
Solution Approach 2:
The patent transitions from sequential verification to parallel verification by adding a temporal dimension. Multiple verification operations execute simultaneously across different circuit portions, transforming the verification process from a single-dimensional sequential scan to a multi-dimensional parallel processing approach, significantly reducing verification time.
2Reliability
If computational resources are increased to handle larger circuit designs, then verification capability improves, but resource consumption increases linearly with circuit size
Solution Approach 1:
The evaluation system is designed as a universal verification platform that can handle various circuit designs of different sizes. The same evaluation system with instruction memory circuitry, interconnect circuitry, and operation circuitry can verify both small and large circuit designs, eliminating the need to proportionally increase resources with circuit size.
Solution Approach 2:
The system performs preliminary compilation of the circuit design into an evaluation format that can be efficiently processed. By pre-processing and organizing the circuit design data structure before verification, the system reduces the computational burden during actual verification, allowing efficient handling of large circuits without linear resource consumption.
3Reliability
If a 4-state model is used for simulation, then design intent verification is achieved, but computational intensity increases
Solution Approach 1:
The patent replaces traditional sequential computational methods with a parallel hardware evaluation system. The evaluation system uses dedicated operation circuitry that can simultaneously process multiple 4-state operations, substituting the mechanical sequential computation with a parallel hardware architecture that maintains design intent verification while reducing computational intensity through concurrent processing.
Data Source
AI summary
A processing system for validating a circuit design, the processing system includes a flow processor, and an evaluation system coupled with the flow processor. The flow processor generates instructions from the circuit design. The evaluation system includes instruction memory circuitry receives the instructions from the flow processor and generate control signals, and interconnect circuitry receives the control signals routes a plurality of values based on the control signals. Each of the plurality of values having one of four states. The evaluation further includes operation circuitry that receives the plurality of values and the control signals, performs one or more operations of the circuit design with the plurality of values based on the control signals, and outputs operation values based on performing the one or more operations, the operation values indicative of an error within the circuit