Clock-Aware Simulation Vector Processing for 4-State Circuit Verification
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Solution Overview
Problem
Existing logic simulation processes for verifying circuit designs are computationally intensive, especially with the increase in circuit size, and the use of 4-state models further exacerbates this issue, requiring more resources and time to verify functional correctness and design intent.
Innovation Solution
A simulation vector processor system employing a parallel hardware implementation and a 4-state model to simulate circuit operations, utilizing a flow processor, evaluation circuit, and interconnect circuitry to efficiently verify the functional correctness and design intent of DUVs, with operators supporting 4-state values and parallel operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional logic simulation processes are used to verify circuit designs, then functional correctness can be verified, but the verification time and computation resources increase significantly with circuit size
Solution Approach 1:
The patent replaces traditional software-based logic simulation with a hardware-based simulation vector processor system. This substitution of mechanical/computational approach with hardware implementation enables parallel processing of circuit verification, dramatically reducing verification time while maintaining functional correctness checking capabilities through dedicated hardware circuits that evaluate logic functions simultaneously
Solution Approach 2:
The simulation vector processor divides the circuit verification task into multiple parallel evaluation circuits, each handling specific logic functions. The system segments the verification process into independent parallel operations that can be executed simultaneously, breaking down the monolithic simulation task into manageable concurrent sub-tasks that reduce overall verification time
2Measurement precision
If 4-state models are used in logic simulation, then more comprehensive functional verification is achieved, but computation resources and processing time are further increased
Solution Approach 1:
The patent replaces software-based 4-state simulation with hardware-based evaluation circuits that natively support 4-state logic values (0, 1, X, Z). This hardware implementation directly manipulates 4-state values through dedicated logic circuits, maintaining comprehensive functional verification capabilities while reducing computational overhead by eliminating the need for software interpretation and complex data structure management
Solution Approach 2:
The system changes the operational parameters by implementing dedicated hardware circuits that operate natively on 4-state values rather than converting between different state representations. This parameter change enables direct manipulation of 4-state logic without additional computational overhead, maintaining verification comprehensiveness while reducing resource consumption through optimized hardware-level operations
3Adaptability or versatility
If circuit design size increases, then more comprehensive design verification is possible, but the amount of computation resources required increases proportionally
Solution Approach 1:
The simulation vector processor employs multiple parallel evaluation circuits that can be configured to handle different portions of a large circuit design. Each evaluation circuit processes specific logic functions in parallel, allowing the system to scale verification capability with circuit size while maintaining constant resource utilization per circuit element through distributed parallel processing
Solution Approach 2:
The evaluation circuits are designed with universal functionality to handle multiple logic operations (AND, OR, NOT, XOR, and other boolean functions) through a single reconfigurable hardware structure. This multi-functionality allows the same hardware resources to verify different aspects of circuit designs, enabling comprehensive verification of large circuits without proportionally increasing computation resources
Data Source
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AI summary
A processing system for validating a circuit design, the processing system includes a flow processor, and an evaluation system coupled with the flow processor. The flow processor generates instructions from the circuit design. The evaluation system includes instruction memory circuitry receives the instructions from the flow processor and generate control signals, and interconnect circuitry receives the control signals routes a plurality of values based on the control signals. Each of the plurality of values having one of four states. The evaluation further includes operation circuitry that receives the plurality of values and the control signals, performs one or more operations of the circuit design with the plurality of values based on the control signals, and outputs operation values based on performing the one or more operations, the operation values indicative of an error within the circuit design.