Clock-Based Soft-Start Circuit for DC-DC Converters

The patent transitions from using time-based control (which requires many counter bits for long durations) to frequency-based control. By controlling the clock frequency that drives the counter, the soft-start time can be extended without increasing the counter bit width, thus avoiding chip size expansion while maintaining effective inrush current restraint.

The patent changes the control parameter from time duration (number of clock cycles) to clock frequency. By adjusting the frequency of the clock signal, the soft-start period can be extended or reduced without requiring additional counter bits, thereby resolving the contradiction between extended soft-start time and chip size.

The patent moves the control dimension from the counter width (spatial dimension) to the clock frequency (temporal dimension). This allows extended soft-start time control without increasing the number of counter bits, thereby avoiding the associated current consumption increase while maintaining the full timing control range.

By changing the control parameter from counter bit width to clock frequency, the patent enables extended soft-start time control without increasing the hardware resources. The current consumption remains constant because the counter size does not increase, while the timing range is extended through frequency adjustment.

The patent replaces the passive capacitor-based timing mechanism with an active digital counter driven by a clock signal. This substitution maintains circuit simplicity while dramatically improving timing control precision, as the counter can accurately count clock cycles to achieve precise soft-start timing.

The patent changes the timing control mechanism from analog capacitor charge/discharge to digital clock counting. This parameter change enables precise timing control through programmable clock frequencies and counter values, while the overall circuit remains simple and easy to implement.